cache_stat.c

ml-rsim 多处理器模拟器 支持类bsd操作系统

      YS__statmsg(nid, "L1 Data Prefetch Statistics:\n");
      Cache_print_prefetch_stat(nid, &(pstat->l1dp));
    }
  
  if (pstat->l2p.total > 0)
    {
      YS__statmsg(nid, "L2 Prefetch Statistics:\n");
      Cache_print_prefetch_stat(nid, &(pstat->l2p));
    }

  /* Stalls because of contention on MSHRs --------------------------------*/
  if (cparam.collect_stats > 1)
    {
      YS__statmsg(nid, "L1 Instruction MSHR Stall:\n");
      CondPrintOne(nid, "  write after read:\t%lld",pstat->l1istall.war);
      CondPrintOne(nid, "  full mshr:       \t%lld",pstat->l1istall.full);
      CondPrintOne(nid, "  cohe pending:    \t%lld",pstat->l1istall.cohe);
      CondPrintOne(nid, "  too many coal:   \t%lld",pstat->l1istall.coal);
      CondPrintOne(nid, "  releasing:       \t%lld",pstat->l1istall.release);
      CondPrintOne(nid, "  flush/purge:     \t%lld", pstat->l1istall.flush);

      YS__statmsg(nid, "L1 Data MSHR Stall:\n");
      CondPrintOne(nid, "  write after read:\t%lld",pstat->l1dstall.war);
      CondPrintOne(nid, "  full mshr:       \t%lld",pstat->l1dstall.full);
      CondPrintOne(nid, "  cohe pending:    \t%lld",pstat->l1dstall.cohe);
      CondPrintOne(nid, "  too many coal:   \t%lld",pstat->l1dstall.coal);
      CondPrintOne(nid, "  releasing:       \t%lld",pstat->l1dstall.release);
      CondPrintOne(nid, "  flush/purge:     \t%lld",pstat->l1dstall.flush);

      YS__statmsg(nid, "\nL2 MSHR Stall:\n");      
      CondPrintOne(nid, "  write after read:\t%lld",pstat->l2stall.war);
      CondPrintOne(nid, "  full mshr:       \t%lld",pstat->l2stall.full);
      CondPrintOne(nid, "  cohe pending:    \t%lld",pstat->l2stall.cohe);
      CondPrintOne(nid, "  too many coal:   \t%lld",pstat->l2stall.coal);
      CondPrintOne(nid, "  releasing:       \t%lld",pstat->l2stall.release);
      CondPrintOne(nid, "  flush/purge:     \t%lld",pstat->l2stall.flush);
    }
  
  /*-----------------------------------------------------------------------*/
  
  if ((pwbuf->stall_wb_full) || (pwbuf->stall_match))
    YS__statmsg(nid, "\nL1 Write Buffer Statistics\n\n");
  
  if (pwbuf->stall_wb_full)
    YS__statmsg(nid, "  stall         \t%d\t",   pwbuf->stall_wb_full);
  if (pwbuf->stall_match)
    YS__statmsg(nid, "  read match    \t%d\n\n", pwbuf->stall_match);
}




  
/*===========================================================================
 * Print statistics for one type of request. (read, write, rmw, etc.)
 * A request is classified as one of the following hit types: 
 * L1 hit, L2 hit, and cache miss (memory hit). 
 * Each cache miss is further split into the following types: 
 * coherence miss, cold miss, conflict miss, and capacity miss.
 */

void Cache_print_one_stat(int nid, char *name,
			  ref_stat_t *oneref,
			  ref_stat_t *total)
{
  static char *MissTypeNames[NUM_CACHE_MISS_TYPES] =
  {
    "generic misses  ",
    "cold misses     ",
    "conflict misses ",
    "capacity misses ",
    "coherency misses"
  };

  int i;

  if (oneref->count <= 0)
    return;

  YS__statmsg(nid, "%s %lld\n", name, oneref->count);

  if (oneref->hits[L1IHIT])
    YS__statmsg(nid,
		"  L1 I-Cache Hits:     %12lld  (%6.2f%%)   Average Cycles:  %8lld\n",
		oneref->hits[L1IHIT],
		100.0 * oneref->hits[L1IHIT]/oneref->count,
		(int)oneref->hitcycles[L1IHIT]/oneref->hits[L1IHIT]);

  if (oneref->hits[L1DHIT])
    YS__statmsg(nid,
		"  L1 D-Cache Hits:     %12lld  (%6.2f%%)   Average Cycles:  %8lld\n",
		oneref->hits[L1DHIT],
		100.0 * oneref->hits[L1DHIT]/oneref->count,
		(int)oneref->hitcycles[L1DHIT]/oneref->hits[L1DHIT]);

  if (oneref->hits[L2HIT] > 0)
    YS__statmsg(nid,
		"  L2 Hits:             %12lld  (%6.2f%%)   Average Cycles:  %8lld\n",
		oneref->hits[L2HIT],
		100.0 * oneref->hits[L2HIT]/oneref->count,
		(int)oneref->hitcycles[L2HIT]/oneref->hits[L2HIT]);

  if (oneref->hits[MEMHIT])
    {
      YS__statmsg(nid,
		  "  Misses:              %12lld  (%6.2f%%)\n",
		  oneref->hits[MEMHIT],
		  100.0 * oneref->hits[MEMHIT]/oneref->count);
      YS__statmsg(nid,
		  "  Miss Cycles:         %12lld              Average Latency: %8lld\n",
		  (int)oneref->hitcycles[MEMHIT] / oneref->hits[MEMHIT],
		  (int)oneref->mlatency / oneref->hits[MEMHIT]);
    }

  for (i = 0; i < NUM_CACHE_MISS_TYPES; i++)
    if (oneref->l1imisses[i] > 0)
      YS__statmsg(nid,
		  "  L1I %s %12lld\n",
		  MissTypeNames[i], oneref->l1imisses[i]);

  for (i = 0; i < NUM_CACHE_MISS_TYPES; i++)
    if (oneref->l1dmisses[i] > 0)
      YS__statmsg(nid,
		  "  L1D %s %12lld\n",
		  MissTypeNames[i], oneref->l1dmisses[i]);

  for (i = 0; i < NUM_CACHE_MISS_TYPES; i++)
    if (oneref->l2misses[i] > 0)
      YS__statmsg(nid,
		  "  L2 %s  %12lld\n",
		  MissTypeNames[i], oneref->l2misses[i]);

  
  /* Add to "total" if necessary ------------------------------------------*/
  if (total)
    {
      total->count += oneref->count;
      for (i = 0; i < UNKHIT; i++)
	{
	  total->hits[i] += oneref->hits[i];
	  total->hitcycles[i] += oneref->hitcycles[i];
	}
      
      for (i = 0; i < NUM_CACHE_MISS_TYPES; i++)
	{
	  total->l1imisses[i] += oneref->l1imisses[i];
	  total->l1dmisses[i] += oneref->l1dmisses[i];
	  total->l2misses[i]  += oneref->l2misses[i];
	}
      
      total->mlatency += oneref->mlatency;
    }
  
  YS__statmsg(nid, "\n");
}



/*===========================================================================
 * Print prefetch statistics.
 */

void Cache_print_prefetch_stat(int nid, prefetch_stat_t *pp)
{
  YS__statmsg(nid, "  Total:       \t%12lld\t", pp->total);
  YS__statmsg(nid, "  dropped:     \t%12lld\n", pp->dropped);
  YS__statmsg(nid, "  unnecessary: \t%12lld\t", pp->unnecessary);
  YS__statmsg(nid, "  issued:      \t%12lld\n", pp->issued);
  YS__statmsg(nid, "  useless:     \t%12lld \t(%.2f%%)\n", 
	      pp->useless, 100.0*pp->useless / pp->issued);
  YS__statmsg(nid, "  useful:      \t%12lld \t(%.2f%%)\n", 
	      pp->useful, 100.0*pp->useful / pp->issued);
  YS__statmsg(nid, "  damaging:    \t%12lld \t(%.2f%%)\n", 
	      pp->damaging, 100.0*pp->damaging / pp->issued);

  if (pp->late)
    YS__statmsg(nid, "  late:        \t%12lld \t(Average: %.2f cycles)\n", 
		pp->late, pp->lateness / pp->late);

  if (pp->early)
    YS__statmsg(nid, "  early:       \t%12lld \t(Average: %.2f cycles)\n", 
		pp->early, pp->earliness / pp->early);
  YS__statmsg(nid, "\n");
}



/*===========================================================================
 * clear all cache stats 
 */

void Cache_stat_clear(int nid, int pid)
{
  if (cparam.collect_stats == 0)
    return;

  memset((char*)PID2L2C(nid, pid)->pstats, 0, sizeof(CacheStat));

  PID2WBUF(nid, pid)->stall_wb_full = 0;
  PID2WBUF(nid, pid)->stall_match   = 0;
}




/*===========================================================================
 * Print cache configuration. (need more?)
 */

void Cache_print_params(int nid)
{
  YS__statmsg(nid, "L1 Instruction Cache Configuration\n");

  if (cparam.L1I_perfect)
    YS__statmsg(nid,
		"  size:           %4d kbytes (perfect I-cache with 100%% hit rate)\n\n", cparam.L1I_size);
  else
    {
      YS__statmsg(nid,
		  "  size:           %4d kbytes\n", cparam.L1I_size);
      YS__statmsg(nid,
		  "  line size:      %4d bytes\t", cparam.L1I_line_size);
      YS__statmsg(nid,
		  "associativity: %4d\n", cparam.L1I_set_size);
      YS__statmsg(nid,
		  "  request queue:  %4d\t\tports:         %4d\n",
		  cparam.L1I_req_queue, cparam.L1I_port_num);
      YS__statmsg(nid,
		  "  MSHR count:     %4d\n", cparam.L1I_mshr_num);
      YS__statmsg(nid,
		  "  delay:          %4d cycles\tfrequency:     %4d\n",
		  cparam.L1I_tag_delay, cparam.frequency);
      YS__statmsg(nid,
		  "  prefetch:        %s\n\n",
		  cparam.L1I_prefetch ? " on" : "off");
    }
      
  YS__statmsg(nid,
	      "L1 Data Cache Configuration\n");

  if (cparam.L1D_perfect)
    YS__statmsg(nid,
		"  size:           %4d kbytes (perfect D-cache with 100%% hit rate)\n\n", cparam.L1D_size);
  else
    {
      YS__statmsg(nid,
		  "  size:           %4d kbytes\n", cparam.L1D_size);
      YS__statmsg(nid,
		  "  line size:      %4d bytes\t", cparam.L1D_line_size);
      YS__statmsg(nid,
		  "associativity: %4d\n", cparam.L1D_set_size);
      YS__statmsg(nid,
		  "  request queue:  %4d\t\tports:         %4d\n",
		  cparam.L1D_req_queue, cparam.L1D_port_num);
      YS__statmsg(nid,
		  "  MSHR count:     %4d\n", cparam.L1D_mshr_num);
      YS__statmsg(nid,
		  "  delay:          %4d cycles\tfrequency:     %4d\n",
		  cparam.L1D_tag_delay, cparam.frequency);
      YS__statmsg(nid,
		  "  prefetch:        %s\n\n",
		  cparam.L1D_prefetch ? " on" : "off");
    }
      
  
  YS__statmsg(nid, "L2 Cache Configuration\n");
      
  if (cparam.L2_perfect)
    YS__statmsg(nid,
		"  Size:          %4d kbytes (perfect L-2 cache with 100%% hit rate)\n\n", cparam.L2_size);
  else
    {
      YS__statmsg(nid,
		  "  size:           %4d kbytes\n",
		  cparam.L2_size);
      YS__statmsg(nid,
		  "  line size:      %4d bytes\t",
		  cparam.L2_line_size);
      YS__statmsg(nid,
		  "associativity: %4d\n",
		  cparam.L2_set_size);
      YS__statmsg(nid,
		  "  request queue:  %4d\t\tports:         %4d\n",
		  cparam.L2_req_queue, cparam.L2_port_num);
      YS__statmsg(nid,
		  "  MSHR count:     %4d\n", cparam.L2_mshr_num);
      YS__statmsg(nid,
		  "  tag delay:      %4d cycles\tdata delay:    %4d\n",
		  cparam.L2_tag_delay, cparam.L2_data_delay);
      YS__statmsg(nid,
		  "  frequency:      %4d\n",
		  cparam.frequency);
      YS__statmsg(nid,
		  "  prefetch:        %s\n\n",
		  cparam.L2_prefetch ? " on" : "off");
    }
}