cache_stat.c

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#include <string.h>
#include <malloc.h>
#include "Processor/simio.h"
#include "Processor/tlb.h"
#include "sim_main/simsys.h"
#include "Caches/system.h"
#include "Caches/req.h"
#include "Caches/cache.h"
#include "Caches/pipeline.h"


/* Private functions */
void Cache_print_one_stat      (int nid, char *name, ref_stat_t *oneref,
			        ref_stat_t *total);
void Cache_print_prefetch_stat (int nid, prefetch_stat_t *pp);


/* Conditional print: print only if the "var" is not zero */
#define CondPrintOne(nid, format, var) 	\
	if (var > 0)			\
	   YS__statmsg(nid, format, var);




/*===========================================================================
 * Collect statistics for each request. It's called when memory system
 * finishes a request and is releasing the control to processor. Note 
 * that the "hit_type" and "miss_type" should have been set with correct 
 * values before this function.
 */ 

void Cache_stat_set(CACHE *captr, REQ *req)
{
  ref_stat_t *rstat;

  /*
   * Use a slight different collecting method for uncached requests.
   */
  if (tlb_uncached(req->memattributes))
    {
      if (req->prcr_req_type == WRITE)
	{
	  captr->pstats->iowrite.count++;
	  captr->pstats->iowrite.mlatency += YS__Simtime - req->issue_time;
	}
      else
	{
	  captr->pstats->ioread.count++;
	  captr->pstats->ioread.mlatency += YS__Simtime - req->issue_time;
	}
      return;
    }

  
  if (req->hit_type == UNKHIT)
    YS__errmsg(captr->nodeid,
	       "Cache_stat_set: Unknow hit type %i for a retired request 0x%08X.", req->hit_type, req->paddr);


  /*
   * Prefetch statistics collection is dispersed among functions in
   * l1cache.c l2cache.c.  
   */
  if (req->prefetch)
    return;

  switch (req->prcr_req_type)
    {
    case READ:
      if (req->ifetch)
	rstat = &(captr->pstats->ifetch);
      else
	rstat = &(captr->pstats->read);
      break;

    case WRITE:
      rstat = &(captr->pstats->write);
      break;

    case RMW:
      rstat = &(captr->pstats->rmw);
      break;

    case FLUSHC:
      /*
       * Flush and purge don't care about cache misses.
       */
      rstat = &(captr->pstats->flush);
      rstat->count++;
      rstat->hits[req->hit_type]++;
      rstat->hitcycles[req->hit_type] += YS__Simtime - req->issue_time;
      return;

    case PURGEC:
      rstat = &(captr->pstats->purge);
      rstat->count++;
      rstat->hits[req->hit_type]++;
      rstat->hitcycles[req->hit_type] += YS__Simtime - req->issue_time;
      return;

    default:
      YS__errmsg(captr->nodeid, "Cache_stat_set(): unknown req_type %d.", req->prcr_req_type);
    }

  rstat->count++;
  rstat->hits[req->hit_type]++;
  rstat->hitcycles[req->hit_type] += YS__Simtime - req->issue_time;


  /*
   * If it's an L1 cache miss
   */
  if (req->hit_type >= L2HIT)
    if (req->ifetch)
      rstat->l1imisses[req->miss_type1]++;
    else
      rstat->l1dmisses[req->miss_type1]++;


  /*
   * If it's an L2 cache miss, count the memory latency.
   */
  if (req->hit_type >= MEMHIT)
    {
      rstat->l2misses[req->miss_type2]++;
      rstat->mlatency += req->bus_return_time - req->bus_start_time;
    }
}



/*===========================================================================
 * Report statistics for a cache module. L1 and L2 cache share
 * the same statistics structure.
 */

void Cache_stat_report(int nid, int pid)
{
  CacheStat *pstat = PID2L2C(nid, pid)->pstats;
  WBUFFER   *pwbuf = PID2WBUF(nid, pid);
  int                issuedprefs;
  ref_stat_t         total;

  if (cparam.collect_stats == 0)
    return;

  YS__statmsg(nid, "Cache Statistics\n\n");


  if (pstat->read.count <= 0)
    return;

  /* Each type of access: READ, WRITE, RMW, FLUSH, PURGE. more? -----------*/
  memset((char *)&(total), 0, sizeof(total));
  Cache_print_one_stat(nid,"Total Instr. Fetches: ",&(pstat->ifetch),&total);
  Cache_print_one_stat(nid,"Total Reads:          ",&(pstat->read), &total);
  Cache_print_one_stat(nid,"Total Writes:         ",&(pstat->write),&total);
  Cache_print_one_stat(nid,"Total RMWs:           ",&(pstat->rmw),  &total);
  Cache_print_one_stat(nid,"Total Flushes:        ",&(pstat->flush),0);
  Cache_print_one_stat(nid,"Total Purges:         ",&(pstat->purge),0);
  Cache_print_one_stat(nid,"Total Accesses:       ",&total,         0);
  CondPrintOne(nid, "Snoop Requests: %lld\n\n", pstat->snoop_requests);

  /* I/O (i.e., uncached processor requests) */
  if (pstat->ioread.count)
    YS__statmsg(nid,
		"I/O read:   %12lld\taverage latency: %8.2f\n",
		pstat->ioread.count,
		pstat->ioread.mlatency / pstat->ioread.count);
  
  if (pstat->iowrite.count)
    YS__statmsg(nid,
		"IO write:   %12lld\taverage latency: %8.2f\n",
		pstat->iowrite.count,
		pstat->iowrite.mlatency / pstat->iowrite.count);

  /*
   * Conflicts. Pay attention to whether a two-level cache hierarchy
   * or a one-level cache hierarchy is being simulated. 
   */
  YS__statmsg(nid,
	      "L1 Instruction Total Conflicts: %12lld\n",
	      pstat->shcl_victims1i+pstat->prcl_victims1i+pstat->prdy_victims1i);
  YS__statmsg(nid,
	      "  pr_clean:                     %12lld\n",
	      pstat->prcl_victims1i);
  YS__statmsg(nid,
	      "  sh_clean:                     %12lld\n",
	      pstat->shcl_victims1i);
  YS__statmsg(nid,
	      "  pr_dirty:                     %12lld\n",
	      pstat->prdy_victims1i);

  YS__statmsg(nid,
	      "L1 Data Total Conflicts:        %12lld\n",
	      pstat->shcl_victims1d+pstat->prcl_victims1d+pstat->prdy_victims1d);
  YS__statmsg(nid,
	      "  pr_clean:                     %12lld\n",
	      pstat->prcl_victims1d);
  YS__statmsg(nid,
	      "  sh_clean:                     %12lld\n",
	      pstat->shcl_victims1d);
  YS__statmsg(nid,
	      "  pr_dirty:                     %12lld\n",
	      pstat->prdy_victims1d);

  YS__statmsg(nid,
	      "L2 Total Conflicts:             %12lld\n",
	      pstat->shcl_victims2+pstat->prcl_victims2+pstat->prdy_victims2);
  YS__statmsg(nid,
	      "  pr_clean:                     %12lld\n",
	      pstat->prcl_victims2);
  YS__statmsg(nid,
	      "  sh_clean:                     %12lld\n",
	      pstat->shcl_victims2);
  YS__statmsg(nid,
	      "  pr_dirty:                     %12lld\n",
	      pstat->prdy_victims2);

  YS__statmsg(nid, "\n");

  
  /* Statistics for speculative loads -------------------------------------*/
  if (pstat->sl1.total > 0)
    {
      YS__statmsg(nid, "L1 Speculative Load Statistics:\n");
      Cache_print_prefetch_stat(nid, &(pstat->sl1));
    }

  if (pstat->sl2.total > 0)
    {
      YS__statmsg(nid, "L2 Speculative Load Statistics:\n");
      Cache_print_prefetch_stat(nid, &(pstat->sl2));
    }

  
  /* Statistics for prefetch ----------------------------------------------*/
  if (pstat->l1ip.total > 0)
    {
      YS__statmsg(nid, "L1 Instruction Prefetch Statistics:\n");
      Cache_print_prefetch_stat(nid, &(pstat->l1ip));
    }
  
  if (pstat->l1dp.total > 0)
    {