cache.h

ml-rsim 多处理器模拟器 支持类bsd操作系统

  int       inq_empty;          /* any REQs on input queues? */

  /* Pipelined cache structure */

  struct YS__Pipeline **data_pipe;     /* For the data RAM array pipes       */
  struct YS__Pipeline **tag_pipe;      /* For the tag array pipes            */
  int    num_in_pipes;                 /* number of accesses in pipes        */

  /* Bus interface, (used by l2 cache only) */

  DLinkQueue reqbuffer;
  LinkQueue  outbuffer;
  LinkQueue  arbwaiters;
  short      arbwaiters_count;

  /* Control or status variables */

  short    stall_request;     /* stop processing requests                   */
  short    stall_cohe;        /* stop processing coherence requests         */
  short    stall_reply;       /* stop processing replies                    */

  REQ    *cohe_reply;         /* only one data coherence reply is allowed   */
  REQ    *data_cohe_pending;
  REQ    *pending_writeback;
  REQ    *pending_request;

  /*
   * Statistics. For one L1 processor, L1 and L2 cache share the same
   * statistics data structure. That's why we use a pointer here.
   */
  CacheStat *pstats;           /* statistics                                 */
  STATREC   *pref_lateness;    /* extent to which late prefetches are late   */
  STATREC   *pref_earliness;   /* length of time useful prefetches sit in    */
  struct CapConfDetector *ccd; /* Capacity-conflict miss detector            */
} CACHE;




/* 
 * write buffer declaration 
 */
typedef struct YS__WBuffer
{
  LinkQueue  write_queue;    /* Outstanding write requests                   */
  LinkQueue  inqueue;        /* The input queue contains requests for L1     */
  int        inq_empty;      /* Is input queue empty                         */
  int        num_in_pipes;   /* Is write_queue empty                         */

  int stall_wb_full;         /* # of times requests stalled because WB full  */
  int stall_match;           /* # of read requests matching prior writes     */
} WBUFFER;




/**************************************************************************/ 
/********************* Global (exported) variables ************************/
/**************************************************************************/


extern CACHE   **L2Caches;
extern CACHE   **L1ICaches;
extern CACHE   **L1DCaches;
extern WBUFFER **WBuffers;
extern int      *L1IQ_FULL;
extern int      *L1DQ_FULL;


extern int L1I_NUM_PORTS;
extern int L1D_NUM_PORTS;
extern int L2_NUM_PORTS;

extern int L1I_TAG_DELAY;       /* L1 I-cache tag array access times         */
extern int L1I_TAG_PIPES;       /* Number of L1 I-cache tag array pipelines  */
extern int L1I_TAG_PORTS[];     /* Number of L1 I-cache ports to tag array   */

extern int L1D_TAG_DELAY;       /* L1 D-cache tag array access times         */
extern int L1D_TAG_PIPES;       /* Number of L1 D-cache tag array pipelines  */
extern int L1D_TAG_PORTS[];     /* Number of L1 D-cache ports to tag array   */

extern int L2_TAG_DELAY;        /* L2 cache tag array access times           */
extern int L2_TAG_PIPES;        /* Number of L2 cache tag array pipelines    */
extern int L2_TAG_PORTS[];      /* Number of L2 cache ports to tag array     */
extern int L2_DATA_DELAY;       /* L2 cache data array access times          */
extern int L2_DATA_PIPES;       /* Number of L2 cache data array pipelines   */
extern int L2_DATA_PORTS[];     /* Number of L2 cache ports to data array    */

extern int L1I_NUM_MSHRS;       /* Number of MSHRs at the L1 I-cache         */
extern int L1D_NUM_MSHRS;       /* Number of MSHRs at the L1 D-cache         */
extern int L2_NUM_MSHRS;        /* Number of MSHRs at the L2 cache           */

extern int MAX_COALS;           /* max. # of request coalesced in one MSHR   */

extern int block_mask1i;
extern int block_mask1d;
extern int block_mask2;

extern int block_shift1i;
extern int block_shift1d;
extern int block_shift2;



/**************************************************************************/ 
/********************* Some useful macros *********************************/
/**************************************************************************/

#define PID2L1I(nid, pid)        (L1ICaches[nid * ARCH_cpus + pid])
#define PID2L1D(nid, pid)        (L1DCaches[nid * ARCH_cpus + pid])
#define PID2L2C(nid, pid)        (L2Caches[nid * ARCH_cpus + pid])
#define PID2WBUF(nid, pid)       (WBuffers[nid * ARCH_cpus + pid])

#define ADDR2BNUM1I(addr)        (addr >> block_shift1i)
#define ADDR2BNUM1D(addr)        (addr >> block_shift1d)
#define ADDR2BNUM2(addr)         (addr >> block_shift2)
#define ADDR2SET(addr)   	 (((addr >> captr->block_shift) & \
                                   captr->idx_mask) << captr->set_shift)
#define PADDR2TAG(paddr)     	 (paddr >> captr->tag_shift)



/**********************************************************************/ 
/* Cache-related functions -- more documentation in .c files          */
/**********************************************************************/

/* 
 * Simulation functions called by cycle-by-cycle simulator in processor
 * module (mainsim.cc).
 */
extern void L1ICacheOutSim (int gid);
extern void L1DCacheOutSim (int gid);
extern void L2CacheOutSim  (int gid);

extern void L1ICacheInSim  (int gid);
extern void L1DCacheInSim  (int gid);
extern void L2CacheInSim   (int gid);



/* Function used by processor to start up a new memory reference */
void DCache_recv_addr      (int, struct instance *, long long, unsigned,
		            int, int, int, int);
void DCache_recv_tlbfill   (int, void (*)(REQ*), unsigned char*, unsigned,
			    void*);
void DCache_recv_barrier   (int);
void ICache_recv_addr      (int, unsigned, unsigned, int, int, unsigned);


/* Cache initialization and search routines. (cache_init.c, cache.c) */
void Cache_init                (void);
void Cache_init_aux            (CACHE *);
int  Cache_search              (CACHE *, unsigned, unsigned, cline_t **);
int  Cache_hit_update          (CACHE *, cline_t *, REQ *);
void Cache_pmiss_update        (CACHE *, REQ *, int, int); 
int  Cache_miss_update         (CACHE *, REQ *, cline_t **, int);   


/* L1 write-buffer routines. (cache_wb.c) */
void L1DCache_wbuffer_init     (WBUFFER *, int nodeid, int pid);
void L1DCache_wbuffer          (int proc_id);
int  L1DCache_wbuffer_search   (WBUFFER * wbufptr, REQ *req, int cohe);
void L1DCacheWBufferSim        (int proc_id);


/* Functions interacting with bus. (cache_bus.c) */
int  Cache_start_send_to_bus   (CACHE *, REQ *);
void Cache_arb_for_bus         (REQ *);
void Cache_in_master_state     (REQ *);
void Cache_send_on_bus         (REQ *);
void Cache_get_cohe_request    (REQ *);
void Cache_get_noncoh_request  (REQ *);
void Cache_get_data_response   (REQ *);
void Cache_get_reply           (REQ *);
void Cache_get_IO_reply        (REQ *);
int  Cache_perfect             (void);
REQ *Cache_check_outbuffer     (CACHE *, REQ *);


/* mmc_stat.c */
void  Cache_stat_set           (CACHE *captr, REQ *req);
void  Cache_print_params       (int);
void  Cache_stat_report        (int, int);
void  Cache_stat_clear         (int, int);


/* Some help functions. (cache_help.c, cache_debug.c) */
REQ  *Cache_make_req           (CACHE *, cline_t *, ReqType);
int   Cache_send_out_req       (LinkQueue *, REQ *);
int   Cache_uncoalesce_mshr    (CACHE *, MSHR *);
int   Cache_free_mshr          (CACHE *captr, MSHR *pmshr);
void  Cache_global_perform     (CACHE *, REQ *, int release_req);
MSHR *Cache_find_mshr          (CACHE *captr, REQ *req);
void  Cache_req_dump           (REQ *, int flag, int);
void  Cache_dump               (int proc_id);

#endif