cache.h

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#ifndef __RSIM_CACHE_H__
#define __RSIM_CACHE_H__

#include "sim_main/stat.h"
#include "Caches/req.h"
#include "Caches/lqueue.h"
#include "Caches/cache_param.h"
#include "Caches/cache_stat.h"


/*************************************************************************/ 
/********************** Cache data structures ****************************/
/*************************************************************************/

/* 
 * Cache line states
 */ 
typedef enum
{
  BAD_LINE_STATE = 0,
  INVALID,
  PR_CL,            /* private clean */
  SH_CL,            /* shared clean */
  PR_DY,            /* private dirty */
  NUM_CACHE_LINE_STATES
} cline_state_t;



/*
 * Cache line data structure  
 */
typedef struct CacheLine
{
  int             index;
  unsigned        tag;           /* tag of cache line */
  unsigned        vaddr;         /* virtual address of cache line */
  cline_state_t   state;         /* state of cache line */
  unsigned short  age;           /* age of access -- used to implement LRU */
  char            mshr_out;      /* upgrade is going on */
  char            pref;          /* used for prefetch stats */
  unsigned        pref_tag_repl; /* used for prefetch stats */
  double          pref_time;     /* used for prefetch stats */
} cline_t;



/*
 * MSHR (miss status hold register) data structure
 */
typedef struct _mshr_
{
  int      valid;               /* Is this MSHR entry valid                  */
  int      setnum;              /* Corresponding set number for the MSHR     */
  REQ     *mainreq;             /* The first request that was sent out       */
  unsigned blocknum;            /* the address tag of mainreq                */
  cline_t *cline;               /* cache line this MSHR is working on        */
  int      misscache;           /* cache hit status                          */

  double   demand;              /* time of first demand access               */
  REQ     *pending_cohe;        /* The first request that was sent out       */
  unsigned stall_WAR:1,         /* A write after read stall in effect        */
           only_prefs:1,        /* Does this MSHR include only prefetches?   */
           has_writes:1,        /* Need to go to PR_DY or PR_CL              */
           releasing:1,         /* being released                            */
           unused:20,
           pend_opers:8;        /* pending flushes or purges                 */

  REQ     *coal_req[MAX_MAX_COALS]; /* Array of coalesced accesses           */
  short    counter;             /* The number of coalesced accesses          */
  short    next_move;
  struct _mshr_ *next;
} MSHR;




/*
 * The following are the return values from Cache_check_mshr rountines.
 */
typedef enum
{
  NOMSHR,               /* no MSHR involved or needed                        */
  NOMSHR_FWD,           /* does not need an MSHR, send it down               */
  NOMSHR_STALL,         /* stall because no MSHRs left                       */
  NOMSHR_STALL_COHE,    /* can't be serviced because cohe_pend bit is set    */

  MSHR_COAL,            /* coalesce into an old MSHR COHES                   */
  MSHR_NEW,             /* get and need a new MSHR                           */
  MSHR_STALL_WAR,       /* stall because of a WAR                            */
  MSHR_STALL_COHE,      /* stall because of a merged MSHR cohe               */
  MSHR_STALL_COAL,      /* stall because of excessive coalescing             */
  MSHR_STALL_FLUSH,     /* stall because pending flush/purge requests        */
  MSHR_STALL_RELEASE,   /* stall because the MSHR is being released          */
  MSHR_USELESS_FETCH,   /* prefetch useless; line fetch already in progress  */
  MAX_MSHR_TYPES
} MSHR_Response;




/*
 * Data structure for a cache.
 */
typedef struct _cache_
{
  short      nodeid;            /* Node number where module is located       */
  short      procid;            /* processor number where module is located  */
  short      gid;               /* system global processor ID                */
  short      type;              /* either L1CACHE or L2CACHE                 */
  struct _cache_ *l2_partner;   /* for L1 caches - points to L2              */
  struct _cache_ *l1i_partner;  /* for L2 cache, points to L1 I-cache        */
  struct _cache_ *l1d_partner;  /* for L2 cache, points to L1 D-cache        */

  /* Cache configuration variables and facilitator variables ----------------*/

  cline_t *tags;                /* cache line states                         */
  char    *data;                /* data for I-Cache, array of instructions   */
  int      size;                /* cache size                                */
  int      linesz;              /* cache line size                           */
  int      setsz;               /* associativity                             */
  int      num_lines;           /* number of cache lines                     */
  int      replacement;         /* replacement policy                        */
  int      set_mask;            /* (setsz - 1)                               */
  int      set_shift;           /* NumberOfBits(setsz - 1)                   */
  int      idx_mask;            /* ((number of sets) - 1)                    */
  int      idx_shift;           /* NumofOfBits((number of sets) - 1)         */
  int      block_mask;          /* number of bits removed to generate block  */
  int      block_shift;         /* # of shift bits to specify block number   */
  int      tag_shift;           /* # of shift bits to specify tag            */
  
  /* MSHR-related data structure */

  MSHR *mshrs;                  /* MSHR structures                           */
  int   mshr_count;             /* number of MSHRs in use                    */
  int   reqmshr_count;          /* number of MSHRs used by REQUESTs          */
  int   reqs_at_mshr_count;     /* number of REQUESTs at MSHRs               */
  int   max_mshrs;              /* total number of MSHRs in cache            */

  /* Input queues */

  LinkQueue request_queue;
  LinkQueue reply_queue;
  LinkQueue cohe_queue;
  LinkQueue noncohe_queue;
  LinkQueue *cohe_reply_queue;             /* for L2 only */