io_generic.c

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

/*****************************************************************************/
/* I/O device bus interface                                                  */
/*   Accepts uncached transactions, performs the memory operations and       */
/*   passes the request to callback functions provided by the device         */
/*   backend. Device backend is responsible for address range registration,  */
/*   memory allocation and reply initiation.                                 */
/* This does not yet handle coherent or device initiated transactions!       */
/*****************************************************************************/


#include <string.h>
#include <malloc.h>

#include "sim_main/simsys.h"
#include "sim_main/util.h"
#include "sim_main/evlst.h"
#include "Processor/simio.h"
#include "Processor/tlb.h"
#include "Processor/memunit.h"
#include "Processor/pagetable.h"
#include "Caches/system.h"
#include "Caches/cache.h"
#include "Caches/pipeline.h"
#include "IO/addr_map.h"
#include "IO/io_generic.h"
#include "Bus/bus.h"
#include "IO/byteswap.h"


IO_GENERIC *IOs = NULL;


int IO_LATENCY = 1;



/*===========================================================================*/
/* Create an I/O device on every node.                                       */
/* To create anything more useful than this generic device:                  */
/*   register address range in each node via AddrMap_insert()                */
/*   allocate host memory to back this address range via PageTable_insert()  */
/*   register read and write callback function (args: node-ID & request)     */
/*   read callback should return a reply via IO_start_send_to_bus()          */
/*   use read_int, read_char, read_bit etc. to read the value of memory-     */
/*   mapped device storage, or use write_int, write_char, write_bit etc.     */
/*   to update device storage (control registers, buffer ..)                 */
/*===========================================================================*/

void IOGeneric_init(int (*read_func)(REQ*),
		    int (*write_func)(REQ*),
		    int (*reply_func)(REQ*))
{
  int i;
  IO_GENERIC *pio;

  get_parameter("BUS_frequency",      &BUS_FREQUENCY,      PARAM_INT);
  get_parameter("BUS_total_requests", &BUS_TOTAL_REQUESTS, PARAM_INT);
  get_parameter("BUS_io_requests",    &BUS_IO_REQUESTS,    PARAM_INT);
  get_parameter("IO_latency",         &IO_LATENCY,         PARAM_INT);

  if (IOs == NULL)
    IOs = (IO_GENERIC*)malloc(sizeof(IO_GENERIC) * ARCH_numnodes);
  else
    IOs = (IO_GENERIC*)realloc(IOs, sizeof(IO_GENERIC) *
			       ARCH_numnodes * (ARCH_ios+1));
  if (!IOs)
    YS__errmsg(0, "Malloc failed in %s:%i", __FILE__, __LINE__);

  /*-------------------------------------------------------------------------*/

  for (i = 0; i < ARCH_numnodes; i++)
    {
      pio = PID2IO(i, ARCH_cpus + ARCH_ios);

      pio->nodeid = i;
      pio->mid    = ARCH_cpus + ARCH_ios;
      
      lqueue_init(&(pio->arbwaiters), IO_MAX_TRANS);
      pio->arbwaiters_count = 0;

      pio->read_func = read_func;
      pio->write_func = write_func;
      pio->reply_func = reply_func;

      lqueue_init(&(pio->cohqueue), BUS_TOTAL_REQUESTS);

      lqueue_init(&(pio->inqueue), IO_MAX_TRANS);    /*@@@ flow control ! @@@*/
      pio->inpipe = NewPipeline(1, IO_LATENCY * BUS_FREQUENCY, 1,
				IO_LATENCY * BUS_FREQUENCY);
      pio->inq_event  = NewEvent("I/O Device request input",
				 IO_handle_inqueue, NODELETE, 0);
      EventSetArg(pio->inq_event, (char*)IO_INDEX(i, ARCH_cpus + ARCH_ios),
						  sizeof(int));
      
      lqueue_init(&(pio->outqueue), IO_MAX_TRANS);

      pio->outpipe = NewPipeline(1, IO_LATENCY * BUS_FREQUENCY, 1,
				 IO_LATENCY * BUS_FREQUENCY);
      pio->outq_event = NewEvent("I/O Device request output",
				 IO_handle_outqueue, NODELETE, 0);
      EventSetArg(pio->outq_event, (char*)IO_INDEX(i, ARCH_cpus + ARCH_ios),
		  sizeof(int));

      pio->writebacks = NULL;

      IO_scoreboard_init(pio);
    }
}




/*===========================================================================*/
/* broadcast coherent request to all I/O devices                             */
/*===========================================================================*/

void IO_get_cohe_request(REQ *req)
{
  int i;

  for (i = 0; i < ARCH_coh_ios; i++)
    IO_get_request(PID2IO(req->node, i + ARCH_cpus), req);
}



/*===========================================================================*/
/* IO is receiving a request from the bus. Called by bus module.             */
/* Put request in pipeline and wake up other end, unless the pipeline or     */
/* queue were not empty, in which case the handler is already awake.         */
/*===========================================================================*/

void IO_get_request(IO_GENERIC *pio, REQ *req)
{
  if ((req->type == REQUEST) &&
      ((req->req_type == READ_UC) ||
       (req->req_type == WRITE_UC) ||
       (req->req_type == SWAP_UC)))
    {
      if (!AddToPipe(pio->inpipe, req))
	YS__errmsg(req->node, "I/O device %i input pipe full", pio->mid);
    }
  else
    {
      if (lqueue_full(&(pio->cohqueue)))
	YS__errmsg(req->node, "I/O device %i coherency queue full", pio->mid);

      lqueue_add(&(pio->cohqueue), req, req->node);
    }

  if (IsNotScheduled(pio->inq_event))
    schedule_event(pio->inq_event, YS__Simtime + BUS_FREQUENCY);
}



/*===========================================================================*/
/* Woken up when the input pipeline or queue is not empty. Take request off  */
/* the queue and handle it by calling 'GlobalPerform'. Writes requests are   */
/* returned to the pool, if the callback function succedded. For reads it    */
/* generates a generic response, if no callback function is specified.       */
/* Upon success, the request is removed from the queue.                      */
/* Check if pipeline contains an element that needs to go into the queue,    */
/* and reschedule if either pipeline or queue are not empty.                 */
/* Note that this routine can be called when there are no requests in the    */
/* queue yet, in this case it may move a request from the pipeline into the  */
/* queue, or just reschedule itself if the pipeline is deep.                 */
/*===========================================================================*/
  
void IO_handle_inqueue(void)
{
  REQ *req, *creq, *nreq;
  IO_GENERIC *pio = &(IOs[(int)EventGetArg(NULL)]);
  int rc = 0, index;


  /*-------------------------------------------------------------------------*/
  req = lqueue_head(&pio->cohqueue);

  if (req != NULL)
    {
      /* insert our own requests into the scoreboard ------------------------*/
      if ((req->src_proc == pio->mid) &&
	  (req->type == REQUEST) &&
	  (req->req_type != READ_UC) &&
	  (req->req_type != WRITE_UC) &&
	  (req->req_type != SWAP_UC))
	IO_scoreboard_insert(pio, req);
	
      creq = IO_scoreboard_lookup(pio, req);
      rc = 0;

      
      /*---------------------------------------------------------------------*/
      /* snoop all coherent requests:
	 our own requests                 -> EXCL (don't care)
	 snoop miss                       -> EXCL
	 hit READ_CURRENT                 -> EXCL
	 READ_SH hits a pending READ_SH   -> SH
	 READ_SH hits pending WRITEBACK   -> EXCL & upgrade WB to C2C_copy
	 READ_OWN hits pending WRITEBACK  -> EXCL & upgrade WB to C2C_copy
	 
	 stall all snoop hits that are ambiguous:
	 read_shared hits read_own
	 upgrade hits read_own/shared
	 read_own hits read_own/shared
	 any hits to replies in flight, hits to upgraded WRITEBACKS
      */

      /* our own request, or no hit: exclusive ------------------------------*/
      if ((req->src_proc == pio->mid) || (creq == NULL))
	{
          Bus_send_cohe_response(req, REPLY_EXCL);
	  rc = 1;
	}

      /* hit and not our own request: depends on request type ---------------*/
      else
	{
	  /* read_current does not transfer ownership */
	  if ((creq->type == REQUEST) && (creq->req_type == READ_CURRENT))
	    {
	      Bus_send_cohe_response(req, REPLY_EXCL);
	      rc = 1;
	    }
	  
	  /* snoop READ_SHARED ----------------------------------------------*/
	  if ((req->type == REQUEST) && (req->req_type == READ_SH))
	    {
	      /* read_shared hits read_shared: remains shared */
	      if ((creq->type == REQUEST) && (creq->req_type == READ_SH))
		{
		  Bus_send_cohe_response(req, REPLY_SH);
		  rc = 1;
		}

	      /* read_shared hits pending writeback: stall response */
	      if (creq->type == WRITEBACK)
		{
		  rc = 0;
		  /* old code - didn't work
		  Bus_send_cohe_response(req, REPLY_EXCL);
		  req->c2c_copy = 1;
		  creq->type = COHE_REPLY;
		  creq->req_type = REPLY_EXCL;
		  creq->dest_proc = req->src_proc;
		  creq->parent = req;
		  rc = 1;
		  */
		}
	    }

	  
	  /* snoop READ_OWN -------------------------------------------------*/
	  if ((req->type == REQUEST) && (req->req_type == READ_OWN))
	    {
	      /* read_own hits pending writeback: stall response */
	      if (creq->type == WRITEBACK)
		{
		  rc = 0;
		  /* old code - didn't work !
		  Bus_send_cohe_response(req, REPLY_EXCL);
		  req->c2c_copy = 1;
		  creq->type = COHE_REPLY;
		  creq->req_type = REPLY_EXCL;
		  creq->dest_proc = req->src_proc;
		  creq->parent = req;
		  rc = 1;
		  */
		}
	    }

	  /* snoop WRITEPURGE: always OK, but invalidate data */
	  if (req->type == WRITEPURGE)
	    {
	      Bus_send_cohe_response(req, REPLY_EXCL);
	      /* read_shared hits pending writeback: remove pending request */
	      if (creq->type == WRITEBACK)
		{
		  /* remove from outgoing queue */
		}
	    }
	}

      if (rc)
	lqueue_remove(&(pio->cohqueue));
    }

  
  /*-------------------------------------------------------------------------*/
  /* handle requests (uncached only) from inqueue, and move requests from    */
  /* delay pipeline to queue                                                 */
  
  req = lqueue_head(&pio->inqueue);

  
  /*-------------------------------------------------------------------------*/

  if ((req != NULL) && (req->type == REQUEST) && (req->prcr_req_type == WRITE))
    {
      creq = req;
      while (creq)
	{
	  req->perform(creq);
	  creq = creq->parent;
	}

      rc = 1;