realtime_clock.h

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

/*****************************************************************************/
/*                                                                           */
/* Realtime Clock (modeled after various existing chips, e.g. Analog Devices */
/*   Dallas DS1743, SGS M48T02 ...)                                          */
/*   Initialized with true time and incremented every simulator second       */
/*   Stores data and time in BCD format                                      */
/*   2 programmable periodic interrupts (1 ms to 10 s interval)              */
/*                                                                           */
/*****************************************************************************/

#ifndef __RSIM_REALTIME_CLOCK_H__
#define __RSIM_REALTIME_CLOCK_H__

#include "Caches/req.h"
#include "Caches/lqueue.h"
#include "time.h"


#define RTC_STATUS       RTC_BASE_ADDR + 0x00
#define RTC_CONTROL      RTC_BASE_ADDR + 0x01
#define RTC_INT1_CNTL    RTC_BASE_ADDR + 0x02
#define RTC_INT1_VECTOR  RTC_BASE_ADDR + 0x03
#define RTC_INT1_TARGET  RTC_BASE_ADDR + 0x04
#define RTC_INT2_CNTL    RTC_BASE_ADDR + 0x05
#define RTC_INT2_VECTOR  RTC_BASE_ADDR + 0x06
#define RTC_INT2_TARGET  RTC_BASE_ADDR + 0x07
#define RTC_YEAR         RTC_BASE_ADDR + 0x08
#define RTC_MONTH        RTC_BASE_ADDR + 0x09
#define RTC_DATE         RTC_BASE_ADDR + 0x0A
#define RTC_DAY          RTC_BASE_ADDR + 0x0B
#define RTC_HOUR         RTC_BASE_ADDR + 0x0C
#define RTC_MINUTE       RTC_BASE_ADDR + 0x0D
#define RTC_SECOND       RTC_BASE_ADDR + 0x0E


typedef struct
{
  int       nodeid;
  int       mid;

  int       old_write_bit;
  char      old_status;
  int       clock;
  time_t    rt;

  unsigned  vector1;
  unsigned  vector2;
  
  EVENT    *update;

  int       intr1_count;
  double    intr1_start;
  double    intr1_lat_max;
  double    intr1_lat_min;
  double    intr1_lat_avg;

  int       intr2_count;
  double    intr2_start;
  double    intr2_lat_max;
  double    intr2_lat_min;
  double    intr2_lat_avg;
} REALTIME_CLOCK;


extern REALTIME_CLOCK *RTCs;

void RTC_init  (void);

int  RTC_read           (REQ*);
int  RTC_write          (REQ*);
void RTC_event          (void);

void RTC_print_params   (int);
void RTC_stat_report    (int);
void RTC_stat_clear     (int);

void RTC_dump           (int);

#endif