scsi_controller.c

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

/***************************************************************************/
/*                                                                         */
/* Generic SCSI controller module: contains system and SCSI bus interface  */
/* Provides callback routines for the generic I/O device module, callback  */
/* routines for the SCSI bus and a PCI mapping callback. Callbacks are     */
/* forwarded to the specific SCSI adapter module through a set of routines */
/* described in a structure.                                               */
/*                                                                         */
/***************************************************************************/


#include <string.h>
#include <malloc.h>
#include <locale.h>

#include "sim_main/simsys.h"
#include "sim_main/util.h"
#include "sim_main/evlst.h"
#include "Processor/simio.h"
#include "Processor/procstate.h"
#include "Processor/pagetable.h"
#include "Caches/syscontrol.h"
#include "Bus/bus.h"
#include "IO/addr_map.h"
#include "IO/io_generic.h"
#include "IO/pci.h"
#include "IO/ahc.h"
#include "IO/scsi_bus.h"
#include "IO/scsi_controller.h"
#include "IO/scsi_disk.h"
#include "IO/byteswap.h"

#include "../../lamix/mm/mm.h"
#include "../../lamix/kernel/syscontrol.h"
#include "../../lamix/dev/pci/pcireg.h"
#include "../../lamix/dev/pci/pcidevs.h"
#include "../../lamix/dev/ic/aic7xxxreg.h"



struct SCSI_CONTROLLER *SCSI_CONTROLLERs;

int ARCH_scsi_cntrs = 1;
int ARCH_disks      = 1;
int first_scsi_cntr = 0;


void     SCSI_cntl_sequencer   (void);

int      SCSI_cntl_host_read   (REQ*);
int      SCSI_cntl_host_write  (REQ*);
int      SCSI_cntl_host_reply  (REQ*);

void     SCSI_cntl_io_wonbus   (void*, SCSI_REQ*);
void     SCSI_cntl_io_request  (void*, SCSI_REQ*);
void     SCSI_cntl_io_response (void*, SCSI_REQ*);

void     SCSI_cntl_pci_map     (unsigned, int, int, int, int,
				unsigned*, unsigned*);



/*=========================================================================*/
/* Initialize SCSI controller:                                             */
/* Create generic I/O bus interface, initialize SCSI controller structure, */
/* attach to the PCI bridge and setup PCI configuration space, create SCSI */
/* bus and attach to bus as a device, call controller specific init.       */
/*=========================================================================*/

void SCSI_cntl_init(void)
{
  int              i, n, d;
  SCSI_CONTROLLER *pscsi;


  get_parameter("NUMscsi", &ARCH_scsi_cntrs, PARAM_INT);
  get_parameter("NUMdisk", &ARCH_disks, PARAM_INT);

  if (ARCH_scsi_cntrs == 0)
    return;
  
  SCSI_CONTROLLERs = RSIM_CALLOC(SCSI_CONTROLLER,
				 ARCH_numnodes * ARCH_scsi_cntrs);
  if ((!SCSI_CONTROLLERs) && (ARCH_numnodes * ARCH_scsi_cntrs > 0))
    YS__errmsg(0, "Malloc failed at %s:%i", __FILE__, __LINE__);

  /*-----------------------------------------------------------------------*/

  first_scsi_cntr = ARCH_cpus + ARCH_ios;

  for (n = 0; n < ARCH_scsi_cntrs; n++)
    {
      IOGeneric_init(SCSI_cntl_host_read,
		     SCSI_cntl_host_write,
		     SCSI_cntl_host_reply);

      for (i = 0; i < ARCH_numnodes; i++)
	{
	  pscsi = PID2SCSI(i, n + first_scsi_cntr);

	  pscsi->nodeid = i;
	  pscsi->mid    = first_scsi_cntr + ARCH_ios;
	  
	  pscsi->pci_me = PCI_attach(i, first_scsi_cntr + ARCH_ios,
				     SCSI_cntl_pci_map);

	  pscsi->pci_me[0].vendor_id      = swap_short(PCI_VENDOR_ADP);
	  pscsi->pci_me[0].device_id      = swap_short(PCI_PRODUCT_ADP_2945U2W);
	  pscsi->pci_me[0].command        = 0x0000;
	  pscsi->pci_me[0].class_revision = swap_word(
	    (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) |
	    (PCI_SUBCLASS_MASS_STORAGE_SCSI << PCI_SUBCLASS_SHIFT));
	  pscsi->pci_me[0].header_type    = PCI_HDR_DEVICE;
	  pscsi->pci_me[0].interrupt_pin  = 1;


	  /* create and initialize bus interface --------------------------*/

          lqueue_init(&(pscsi->reply_queue),     BUS_TOTAL_REQUESTS);
          lqueue_init(&(pscsi->dma_queue),       BUS_TOTAL_REQUESTS);
          lqueue_init(&(pscsi->interrupt_queue), 1);

	  pscsi->bus_interface = NewEvent("SCSI Bus Interface",
					  SCSI_cntl_bus_interface, NODELETE,0);
	  EventSetArg(pscsi->bus_interface, pscsi, sizeof(pscsi));


	  /* create SCSI bus and put myself on it as device N-1 -----------*/
	  pscsi->scsi_bus = SCSI_bus_init(i, n);
	  pscsi->scsi_id  = SCSI_WIDTH * 8 - 1;
	  pscsi->scsi_me  = SCSI_device_init(pscsi->scsi_bus, pscsi->scsi_id,
					     pscsi,
					     SCSI_cntl_io_wonbus,
					     SCSI_cntl_io_request,
					     SCSI_cntl_io_response,
					     NULL, NULL, NULL, NULL);


      
	  /* create disks -------------------------------------------------*/

	  for (d = 0; d < ARCH_disks; d++)
	    {
	      SCSI_disk_init(pscsi->scsi_bus, d);
	    }

	  if (ARCH_disks > 0)
	    pscsi->scsi_max_target = ARCH_disks - 1;
	  else
	    pscsi->scsi_max_target = 0;
	  pscsi->scsi_max_lun    = 0;

	  /* create actual controller backend -----------------------------*/
	  ahc_init(pscsi, pscsi->scsi_id);
	}
      
      ARCH_ios++;
      ARCH_coh_ios++;
    }
}





/*===========================================================================*/
/* Host Bus Read Callback Function - forward individual requests to          */
/* specific controller and generate reply transaction                        */
/*===========================================================================*/

int SCSI_cntl_host_read(REQ* req)
{
  SCSI_CONTROLLER *pscsi = PID2SCSI(req->node, req->dest_proc);
  REQ             *nreq;

  nreq = req;
  while (nreq != NULL)
    {
      if (pscsi->contr_spec->host_read)
	if (pscsi->contr_spec->host_read(pscsi->controller,
					 nreq->paddr,
					 nreq->size) == 0)
	  return(0);
      nreq = nreq->parent;
    }

  req->type = REPLY;
  req->req_type = REPLY_UC;

  if (lqueue_full(&(pscsi->reply_queue)))
    YS__errmsg(pscsi->nodeid, "SCSI Reply queue full!\n");

  lqueue_add(&(pscsi->reply_queue), req, pscsi->nodeid);

  if (IsNotScheduled(pscsi->bus_interface))
    schedule_event(pscsi->bus_interface, YS__Simtime + BUS_FREQUENCY);

  return(1);
}




/*===========================================================================*/
/* Host Bus Write Callback Function                                          */
/* forward individual requests to specific controller                        */
/*===========================================================================*/

int SCSI_cntl_host_write(REQ* req)
{
  SCSI_CONTROLLER *pscsi = PID2SCSI(req->node, req->dest_proc);
  
  while (req != NULL)
    {
      if (pscsi->contr_spec->host_write)
	if (pscsi->contr_spec->host_write(pscsi->controller,
					  req->paddr,
					  req->size) == 0)
	  return(0);
      req = req->parent;
    }

  return(1);
}



/*===========================================================================*/
/* Host Bus Reply Callback function - do nothing (yet)                       */
/*===========================================================================*/

int SCSI_cntl_host_reply(REQ *req)
{
  return(1);
}




/*===========================================================================*/
/* PCI Map callback function - forward to controller-specific callback       */
/*===========================================================================*/

void SCSI_cntl_pci_map(unsigned address, int node, int module,