dram_init.c

ml-rsim 多处理器模拟器 支持类bsd操作系统

  dparam.databuf_shift = NumOfBits(dparam.num_banks / dparam.num_databufs, 1);
  dparam.databuf_mask  = dparam.num_databufs - 1;
  
  /*
   * Convert DRAM cycles into simulation cycles.
   */

#if 0
  dparam.sa_bus_cycles  *= dparam.frequency;
  dparam.sd_bus_cycles  *= dparam.frequency;
#endif

  dparam.row_hold_time  *= dparam.frequency;
  dparam.refresh_delay  *= dparam.frequency;
  dparam.refresh_period *= dparam.frequency;

  if (dparam.dram_type == SDRAM)
    {
      dparam.dtime.s.CCD    *= dparam.frequency;
      dparam.dtime.s.RRD    *= dparam.frequency;
      dparam.dtime.s.RP     *= dparam.frequency;
      dparam.dtime.s.RAS    *= dparam.frequency;
      dparam.dtime.s.RCD    *= dparam.frequency;
      dparam.dtime.s.AA     *= dparam.frequency;
      dparam.dtime.s.DAL    *= dparam.frequency;
      dparam.dtime.s.DPL    *= dparam.frequency;
      dparam.dtime.s.PACKET *= dparam.frequency;

      dparam.co2d_cycles = dparam.dtime.s.CCD + dparam.dtime.s.RAS + 
	dparam.dtime.s.RCD + dparam.dtime.s.AA + 
	dparam.dtime.s.PACKET;
    }
  else
    {
      dparam.dtime.r.PACKET *= dparam.frequency;
      dparam.dtime.r.RC     *= dparam.frequency;
      dparam.dtime.r.RR     *= dparam.frequency;
      dparam.dtime.r.RP     *= dparam.frequency;
      dparam.dtime.r.CBUB1  *= dparam.frequency;
      dparam.dtime.r.CBUB2  *= dparam.frequency;
      dparam.dtime.r.RCD    *= dparam.frequency;
      dparam.dtime.r.CAC    *= dparam.frequency;
      dparam.dtime.r.CWD    *= dparam.frequency;

      dparam.co2d_cycles = dparam.dtime.r.RCD + dparam.dtime.r.PACKET + 
	dparam.dtime.r.CAC + dparam.dtime.r.RP;
    }
}



/*
 * Every bank is associated with a prioritized waiting queue, and a worker 
 * event which schedules transactions in waiting queue.
 */
void DRAM_bank_init(dram_info_t *pdb, int bid)
{
  dram_bank_t      *pbank = &(pdb->banks[bid]);
  bank_queue_t     *dq    = &(pbank->waiters);
  bank_queue_elm_t *qelms;
  int               i;

  pbank->id        = bid;
  pbank->busy	    = 0;
  pbank->expire    = 0;
  pbank->hitmiss   = 0;
  pbank->last_type = DRAM_READ;
  pbank->chip      = DRAM_bankid_to_chip(pdb, bid);

  /*
   * Initialize the waiting queue.
   */
  if (!(qelms = RSIM_CALLOC(bank_queue_elm_t, dparam.bank_depth)))
    YS__errmsg(0, "malloc failed at %s:%i", __FILE__, __LINE__);

  dq->max  = dparam.bank_depth;
  dq->size = 0;
  dq->head = dq->tail = 0;
  dq->free = 0;
  for (i = 0; i < dq->max; i++)
    {
      qelms[i].next = dq->free;
      dq->free = &(qelms[i]);
    }

  pbank->pevent        = NewEvent("bank", DRAM_bank_done, NODELETE, 0);
  pbank->pevent->uptr1 = pdb;
  pbank->pevent->uptr2 = pbank;
  pbank->pevent->uptr3 = DRAM_bankid_to_databuf(pdb, bid);
}



/*
 * This function must be called before any other functions of 
 * the DRAM module can be used.
 */
void DRAM_init(void)
{
  int           i, j, k;
  dram_info_t   *pdb;
  dram_trans_t  *dtrans;

  /*
   * Read parameters from the designated parameter file.
   */
  DRAM_read_params();

  if (!(DBs = RSIM_CALLOC(dram_info_t, ARCH_numnodes)))
    YS__errmsg(0, "Malloc failed at %s:%i", __FILE__, __LINE__);

  for (i = 0; i < ARCH_numnodes; i++)
    {
      pdb         = &(DBs[i]);
      pdb->nodeid = i;

      /* 
       * Queue up all the dram transactions into a free list.
       */
      if (!(dtrans = RSIM_CALLOC(dram_trans_t, MAX_TRANS * DRAM_MAX_FACTOR)))
	YS__errmsg(i, "Malloc failed at %s:%i", __FILE__, __LINE__);

      lqueue_init(&pdb->freedramlist, MAX_TRANS * DRAM_MAX_FACTOR);
      for (j = 0; j < MAX_TRANS * DRAM_MAX_FACTOR; j++)
	{
	  lqueue_add(&pdb->freedramlist, dtrans, i);
	  dtrans++;
	}

      /*
       * The DRAM backend simulator is not on, we only need a waiting list
       * and an event.
       */
      if (dparam.sim_on == 0)
	{
	  lqueue_init(&pdb->waitlist, MAX_TRANS * DRAM_MAX_FACTOR);
	  pdb->pevent = NewEvent("sabus", DRAM_nosim_done, NODELETE, 0);
	  pdb->pevent->uptr1 = pdb;
	  continue;
	}

      /*
       * Initialize the Slave Address bus.
       */
      pdb->sa_bus.pevent = NewEvent("sabus", DRAM_arrive_smc, NODELETE, 0);
      pdb->sa_bus.pevent->uptr1 = pdb;
      pdb->sa_bus.pevent->uptr2 = &(pdb->sa_bus);

      pdb->sa_bus.waiters = cbuf_alloc(1024 * DRAM_MAX_FACTOR);
      pdb->sa_bus.busy    = 0;
      pdb->sa_bus.count   = 0;
      pdb->sa_bus.waits   = 0;
      pdb->sa_bus.cycles  = 0;
      pdb->sa_bus.wcycles = 0;

      /*
       * Initialize the Slave Data bus.
       */
      pdb->sd_bus.busy_until = 0;
      pdb->sd_bus.count      = 0;
      pdb->sd_bus.waits      = 0;
      pdb->sd_bus.cycles     = 0;
      pdb->sd_bus.wcycles    = 0;
      
      /*
       * Initialize the RD busses
       */
      if (!(pdb->rd_busses = RSIM_CALLOC(dram_rd_bus_t, dparam.rd_busses)))
	YS__errmsg(i, "Malloc failed at %s:%i", __FILE__, __LINE__);

      for (j = 0; j < dparam.rd_busses; j++)
	{
	  dram_rd_bus_t *prdbus = &(pdb->rd_busses[j]);

	  prdbus->busy_until = 0;
	  prdbus->count      = 0;
	  prdbus->waits      = 0;
	  prdbus->cycles     = 0;
	  prdbus->wcycles    = 0;
	}

      /*
       * Initialize the data buffers (Accumulate/Mux Chips).
       */
      if (!(pdb->databufs = RSIM_CALLOC(dram_databuf_t, dparam.num_databufs)))
	YS__errmsg(i, "Malloc failed at %s:%i", __FILE__, __LINE__);

      for (j = 0; j < dparam.num_databufs; j++)
	{
	  dram_databuf_t *pdatabuf = &(pdb->databufs[j]);
	  
	  pdatabuf->cevent = NewEvent("data buffer done",
				     DRAM_databuf_done, NODELETE, 0);
	  pdatabuf->cevent->uptr1 = pdb;
	  pdatabuf->cevent->uptr2 = pdatabuf;

	  pdatabuf->devent = NewEvent("data buffer data ready",
				     DRAM_databuf_data_ready, NODELETE, 0);
	  pdatabuf->devent->uptr1 = pdb;
	  pdatabuf->devent->uptr2 = pdatabuf;

	  pdatabuf->waiters       = cbuf_alloc(1024);
	  pdatabuf->busy          = 0;
	}

      /*
       * Initialize the chips. Each chip has a refreshing event which 
       * efreshs the bank periodically.
       */
      if (!(pdb->chips = RSIM_CALLOC(dram_chip_t, dparam.num_chips)))
	YS__errmsg(i, "Malloc failed at %s:%i", __FILE__, __LINE__);

      for (j = 0; j < dparam.num_chips; j++)
	{
	  dram_chip_t *pchip = &(pdb->chips[j]);

	  pchip->id        = j;
	  pchip->ras_busy  = 0;
	  pchip->cas_busy  = 0;
	  pchip->last_type = DRAM_READ;
	  pchip->last_bank = 0;

	  pchip->refresh_event = NewEvent("chip", DRAM_refresh, NODELETE, 0);
	  pchip->refresh_event->uptr1 = pdb;
	  pchip->refresh_event->uptr2 = pchip;
	  pchip->refresh_event->ival1 = j;
	  pchip->refresh_on           = 0;
	  pchip->refresh_needed       = 0;
	}

      /*
       * Initialize the banks.
       */
      if (!(pdb->banks = RSIM_CALLOC(dram_bank_t, dparam.num_banks)))
	YS__errmsg(i, "Malloc failed at %s:%i", __FILE__, __LINE__);

      for (k = 0; k < dparam.num_banks; k++) 
	DRAM_bank_init(pdb, k);

      pdb->total_bwaiters = 0;
      pdb->total_count = 0;
      pdb->total_cycles = 0;
    }
}



/*
 * Circular Buffers
 */
circbuf_t *cbuf_alloc(int size)
{
  int        bytes   = sizeof(circbuf_t) + ((size - 1) * sizeof(long));
  circbuf_t *the_q   = (circbuf_t *) malloc(bytes);
  int        logsize = ToPowerOf2(size);

  if (logsize != size)
    YS__errmsg(0, "cbuf_alloc: Must be a power of 2");

  if (!the_q)
    YS__errmsg(0, "cbuf_alloc: malloc failure");

  bzero(the_q, bytes);
  the_q->mask = size - 1;
  the_q->size = size;
  return the_q;
}