dram_init.c

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <strings.h>
#include "Processor/simio.h"
#include "sim_main/simsys.h"
#include "Memory/mmc.h"
#include "DRAM/cqueue.h"
#include "DRAM/dram_param.h"
#include "DRAM/dram.h"


/* 
 * Define global variables here. 
 */
dram_info_t  *DBs;      /* Per processor information of DRAM-backend */
dram_param_t  dparam;   /* DRAM-backend parameters */


#ifdef TRACEDRAM
 char     dram_trace_file[128];
 FILE    *dram_trace_fp;
 unsigned dram_trace_count = 0;
#endif



/*
 * Read DRAM-backend-related parameters from the designated parameter file.
 */
void DRAM_read_params(void)
{
  char  tmpbuf[256];

  /* 
   * Switches for debugging/tracing support.
   */
  dparam.sim_on         = 1;
  dparam.latency        = 18;
  dparam.frequency      = 1;
  dparam.scheduler_on   = 1;
  dparam.debug_on       = 0;
  dparam.collect_stats  = 1;
  dparam.trace_on       = 0;
  dparam.trace_max      = 0;

  get_parameter("DRAM_sim_on",        &dparam.sim_on,        PARAM_INT);
  get_parameter("DRAM_latency",       &dparam.latency,       PARAM_INT);
  get_parameter("DRAM_frequency",     &dparam.frequency,     PARAM_INT);
  get_parameter("DRAM_scheduler",     &dparam.scheduler_on,  PARAM_INT);
  get_parameter("DRAM_debug",         &dparam.debug_on,      PARAM_INT);
  get_parameter("DRAM_collect_stats", &dparam.collect_stats, PARAM_INT);
  get_parameter("DRAM_trace_on",      &dparam.trace_on,      PARAM_INT);
  get_parameter("DRAM_trace_max",     &dparam.trace_max,     PARAM_INT);
  
  if (MMC_sim_on() == 0)
    {
      dparam.sim_on = 0;
      dparam.collect_stats = 0;
    }

#ifdef TRACEDRAM
  if (dparam.trace_on)
    {
      if (!get_parameter("DRAM_trace_file", dram_trace_file, PARAM_STRING))
	strcpy(dram_trace_file, "dram_trace");

      if (!(dram_trace_fp = fopen(dram_trace_file, "w")))
	YS__errmsg(0, "Couldn't open dram trace file %s\n", dram_trace_file);
    }
#endif

  /* 
   * DRAM backend organization.
   */
  dparam.sa_bus_cycles  = DRAM_SA_BUS_CYCLES;
  dparam.sd_bus_cycles  = DRAM_SD_BUS_CYCLES;
  dparam.sd_bus_width   = DRAM_SD_BUS_WIDTH;
  dparam.rd_busses      = DRAM_RD_BUSSES;
  dparam.num_databufs   = DRAM_NUM_DATABUFS;
  dparam.critical_word  = DRAM_CRITICAL_WORD;
  dparam.banks_per_chip = DRAM_BANKS_PER_CHIP;
  dparam.num_banks      = DRAM_NUM_BANKS;
  dparam.bank_depth     = DRAM_BANK_DEPTH;
  dparam.interleaving   = 0;
  dparam.max_bwaiters   = dparam.bank_depth * dparam.num_banks;

  get_parameter("DRAM_sa_bus_cycles",  &dparam.sa_bus_cycles,  PARAM_INT);
  get_parameter("DRAM_sd_bus_cycles",  &dparam.sd_bus_cycles,  PARAM_INT);
  get_parameter("DRAM_sd_bus_width",   &dparam.sd_bus_width,   PARAM_INT);
  get_parameter("DRAM_num_smcs",       &dparam.rd_busses,      PARAM_INT);
  get_parameter("DRAM_num_databufs",   &dparam.num_databufs,   PARAM_INT);
  get_parameter("DRAM_critical_word",  &dparam.critical_word,  PARAM_INT);
  get_parameter("DRAM_num_banks",      &dparam.num_banks,      PARAM_INT);
  get_parameter("DRAM_banks_per_chip", &dparam.banks_per_chip, PARAM_INT);
  get_parameter("DRAM_bank_depth",     &dparam.bank_depth,     PARAM_INT);
  get_parameter("DRAM_interleaving",   &dparam.interleaving,   PARAM_INT);
  get_parameter("DRAM_max_bwaiters",   &dparam.max_bwaiters,   PARAM_INT);

  if (dparam.rd_busses > DRAM_MAX_RD_BUSSES)
    YS__errmsg(0, "Too many smcs: %d (DRAM_init)\n", dparam.rd_busses);

  if (dparam.num_databufs > DRAM_MAX_DATABUFS)
    YS__errmsg(0, "Too many data buffers: %d (DRAM_init)\n", dparam.num_databufs);

  if (dparam.num_banks > DRAM_MAX_BANKS)
    YS__errmsg(0, "Too many banks: %d (DRAM_init)\n", dparam.num_banks);

  if (dparam.num_banks % dparam.rd_busses)
    YS__errmsg(0, "num_banks(%d) %% num_smcs(%d) != 0 (DRAM_init)\n",
	       dparam.num_banks, dparam.rd_busses);

  /* 
   * DRAM bank parameters 
   */
  dparam.dram_type      = SDRAM;
  dparam.hot_row_policy = 0;
  dparam.block_size     = DRAM_BLOCK_SIZE;
  dparam.mini_access    = DRAM_MINI_ACCESS;
  dparam.width          = DRAM_WIDTH;
  dparam.row_size       = DRAM_ROW_SIZE;
  dparam.row_hold_time  = DRAM_ROW_HOLD_TIME;
  dparam.refresh_delay  = DRAM_REFRESH_CYCLES;
  dparam.refresh_period = DRAM_REFRESH_PERIOD;
  
  if (get_parameter("DRAM_type", tmpbuf, PARAM_STRING))
    {
      if (!strcmp(tmpbuf, "SDRAM"))
	dparam.dram_type = SDRAM;
      else if (!strcmp(tmpbuf, "RDRAM"))
	dparam.dram_type = RDRAM;
      else
	YS__errmsg(0, "Unknown DRAM type %s\n", tmpbuf);
    }
  
  get_parameter("DRAM_hot_row_policy",   &dparam.hot_row_policy, PARAM_INT);
  get_parameter("DRAM_width",            &dparam.width,          PARAM_INT);
  get_parameter("DRAM_mini_access",      &dparam.mini_access,    PARAM_INT);
  get_parameter("DRAM_block_size",       &dparam.block_size,     PARAM_INT);

  if (dparam.dram_type == SDRAM)
    {
      dparam.dtime.s.CCD    = SDRAM_tCCD;
      dparam.dtime.s.RRD    = SDRAM_tRRD;
      dparam.dtime.s.RP     = SDRAM_tRP;
      dparam.dtime.s.RAS    = SDRAM_tRAS;
      dparam.dtime.s.RCD    = SDRAM_tRCD;
      dparam.dtime.s.AA     = SDRAM_tAA;
      dparam.dtime.s.DAL    = SDRAM_tDAL;
      dparam.dtime.s.DPL    = SDRAM_tDPL;
      dparam.dtime.s.PACKET = SDRAM_tPACKET;
      
      get_parameter("SDRAM_tCCD",    &dparam.dtime.s.CCD,    PARAM_INT);
      get_parameter("SDRAM_tRRD",    &dparam.dtime.s.RRD,    PARAM_INT);
      get_parameter("SDRAM_tRP",     &dparam.dtime.s.RP,     PARAM_INT);
      get_parameter("SDRAM_tRAS",    &dparam.dtime.s.RAS,    PARAM_INT);
      get_parameter("SDRAM_tRCD",    &dparam.dtime.s.RCD,    PARAM_INT);
      get_parameter("SDRAM_tAA",     &dparam.dtime.s.AA,     PARAM_INT);
      get_parameter("SDRAM_tDAL",    &dparam.dtime.s.DAL,    PARAM_INT);
      get_parameter("SDRAM_tDPL",    &dparam.dtime.s.DPL,    PARAM_INT);
      get_parameter("SDRAM_tPACKET", &dparam.dtime.s.PACKET, PARAM_INT);

      get_parameter("SDRAM_row_size",      &dparam.row_size,       PARAM_INT);
      get_parameter("SDRAM_row_hold_time", &dparam.row_hold_time,  PARAM_INT);
      get_parameter("SDRAM_refresh_delay", &dparam.refresh_delay,  PARAM_INT);
      get_parameter("SDRAM_refresh_period",&dparam.refresh_period, PARAM_INT);
    }
  else
    {
      dparam.dtime.r.PACKET = RDRAM_tPACKET;
      dparam.dtime.r.RC     = RDRAM_tRC;
      dparam.dtime.r.RR     = RDRAM_tRR;
      dparam.dtime.r.RP     = RDRAM_tRP;
      dparam.dtime.r.CBUB1  = RDRAM_tCBUB1;
      dparam.dtime.r.CBUB2  = RDRAM_tCBUB2;
      dparam.dtime.r.RCD    = RDRAM_tRCD;
      dparam.dtime.r.CAC    = RDRAM_tCAC;
      dparam.dtime.r.CWD    = RDRAM_tCWD;

      get_parameter("RDRAM_tPACKET", &dparam.dtime.r.PACKET, PARAM_INT);
      get_parameter("RDRAM_tRC",     &dparam.dtime.r.RC,     PARAM_INT);
      get_parameter("RDRAM_tRR",     &dparam.dtime.r.RR,     PARAM_INT);
      get_parameter("RDRAM_tRP",     &dparam.dtime.r.RP,     PARAM_INT);
      get_parameter("RDRAM_tCBUB1",  &dparam.dtime.r.CBUB1,  PARAM_INT);
      get_parameter("RDRAM_tCBUB2",  &dparam.dtime.r.CBUB2,  PARAM_INT);
      get_parameter("RDRAM_tRCD",    &dparam.dtime.r.RCD,    PARAM_INT);
      get_parameter("RDRAM_tCAC",    &dparam.dtime.r.CAC,    PARAM_INT);
      get_parameter("RDRAM_tCWD",    &dparam.dtime.r.CWD,    PARAM_INT);

      get_parameter("RDRAM_row_size",      &dparam.row_size,       PARAM_INT);
      get_parameter("RDRAM_row_hold_time", &dparam.row_hold_time,  PARAM_INT);
      get_parameter("RDRAM_refresh_delay", &dparam.refresh_delay,  PARAM_INT);
      get_parameter("RDRAM_refresh_period",&dparam.refresh_period, PARAM_INT);
    }

  
  /* 
   * The following variables are used to simplify arithmetic operations
   * into bit operations. 
   */
  dparam.num_chips    = dparam.num_banks / dparam.banks_per_chip;
  dparam.width_shift  = NumOfBits(dparam.width, 1);
  dparam.row_shift    = NumOfBits(dparam.row_size * dparam.num_banks, 1);
  dparam.sd_bus_shift = NumOfBits(dparam.sd_bus_width, 1);

  if (!(dparam.interleaving & 1)) /* 0 or 2*/
    dparam.bank_shift = NumOfBits(dparam.block_size, 1);
  else /* 1 or 3 */
    dparam.bank_shift = NumOfBits(dparam.row_size, 1);

  dparam.bank_mask     = dparam.num_banks - 1;
  dparam.chip_shift    = NumOfBits(dparam.banks_per_chip, 1);
  dparam.chip_mask     = dparam.num_chips - 1;
  dparam.rd_bus_shift  = NumOfBits(dparam.num_banks / dparam.rd_busses, 1);
  dparam.rd_bus_mask   = dparam.rd_busses - 1;