📄 comp.rpt
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60 -> - - * * | - - * - | <-- AS103
16 -> * - - - | - - * - | <-- BM0
15 -> * - - - | - - * - | <-- BM1
12 -> * * - - | - - * - | <-- BM2
11 -> - * - - | - - * - | <-- BM3
25 -> - - - * | - - * - | <-- BS0
27 -> - - - * | - - * - | <-- BS1
35 -> - * - - | - - * - | <-- BS100
40 -> - - * - | - - * - | <-- BS101
4 -> - - * - | - - * - | <-- BS102
5 -> - - * * | - - * - | <-- BS103
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------- LC50 AEB
| +----- LC62 ~143~1
| | +--- LC57 ~143~2
| | | +- LC49 ~143~3
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'D'
LC | | | | | A B C D | Logic cells that feed LAB 'D':
LC62 -> * - - - | - - - * | <-- ~143~1
LC57 -> * - - - | - - - * | <-- ~143~2
LC49 -> * - - - | - - - * | <-- ~143~3
Pin
54 -> - * * - | - - - * | <-- AH0
50 -> - - * - | - - - * | <-- AH1
49 -> - - * - | - - - * | <-- AH2
24 -> - - - * | - - - * | <-- AH3
28 -> * - - - | - - - * | <-- AH100
29 -> * - - - | - - - * | <-- AH101
33 -> - * - - | - - - * | <-- AH102
34 -> - * - - | - - - * | <-- AH103
58 -> - - - * | - - - * | <-- AM100
21 -> - - - * | * - - * | <-- AM101
75 -> * - - - | - - - * | <-- AS2
73 -> * - - - | - - - * | <-- AS3
39 -> - * * - | - - - * | <-- BH0
41 -> - - * - | - - - * | <-- BH1
45 -> - - * - | - - - * | <-- BH2
9 -> - - - * | - - - * | <-- BH3
18 -> * - - - | - - - * | <-- BH100
20 -> * - - - | - - - * | <-- BH101
8 -> - * - - | - - - * | <-- BH102
17 -> - * - - | - - - * | <-- BH103
10 -> - - - * | - - - * | <-- BM100
22 -> - - - * | * - - * | <-- BM101
30 -> * - - - | - - - * | <-- BS2
31 -> * - - - | - - - * | <-- BS3
LC1 -> * - - - | - - - * | <-- ~143~4
LC33 -> * - - - | - - - * | <-- ~143~5
LC35 -> * - - - | - - - * | <-- ~143~6
LC36 -> * - - - | - - - * | <-- ~143~7
LC38 -> * - - - | - - - * | <-- ~143~8
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\gongzuo\digital clock\comp.rpt
comp
** EQUATIONS **
AH0 : INPUT;
AH1 : INPUT;
AH2 : INPUT;
AH3 : INPUT;
AH100 : INPUT;
AH101 : INPUT;
AH102 : INPUT;
AH103 : INPUT;
AM0 : INPUT;
AM1 : INPUT;
AM2 : INPUT;
AM3 : INPUT;
AM100 : INPUT;
AM101 : INPUT;
AM102 : INPUT;
AM103 : INPUT;
AS0 : INPUT;
AS1 : INPUT;
AS2 : INPUT;
AS3 : INPUT;
AS100 : INPUT;
AS101 : INPUT;
AS102 : INPUT;
AS103 : INPUT;
BH0 : INPUT;
BH1 : INPUT;
BH2 : INPUT;
BH3 : INPUT;
BH100 : INPUT;
BH101 : INPUT;
BH102 : INPUT;
BH103 : INPUT;
BM0 : INPUT;
BM1 : INPUT;
BM2 : INPUT;
BM3 : INPUT;
BM100 : INPUT;
BM101 : INPUT;
BM102 : INPUT;
BM103 : INPUT;
BS0 : INPUT;
BS1 : INPUT;
BS2 : INPUT;
BS3 : INPUT;
BS100 : INPUT;
BS101 : INPUT;
BS102 : INPUT;
BS103 : INPUT;
-- Node name is 'AEB'
-- Equation name is 'AEB', location is LC050, type is output.
AEB = LCELL( _EQ001 $ _EQ002);
_EQ001 = AH100 & !BH100 & !_LC001 & !_LC033 & !_LC035 & !_LC036 & !_LC038 &
!_LC049 & !_LC057 & !_LC062 & _X001 & _X002 & _X003 & _X004
# !AH100 & BH100 & !_LC001 & !_LC033 & !_LC035 & !_LC036 & !_LC038 &
!_LC049 & !_LC057 & !_LC062 & _X001 & _X002 & _X003 & _X004
# AH101 & !BH101 & !_LC001 & !_LC033 & !_LC035 & !_LC036 & !_LC038 &
!_LC049 & !_LC057 & !_LC062 & _X001 & _X002 & _X003 & _X004
# !AH101 & BH101 & !_LC001 & !_LC033 & !_LC035 & !_LC036 & !_LC038 &
!_LC049 & !_LC057 & !_LC062 & _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!AS3 & BS3);
_X002 = EXP( AS3 & !BS3);
_X003 = EXP(!AS2 & BS2);
_X004 = EXP( AS2 & !BS2);
_EQ002 = !_LC001 & !_LC033 & !_LC035 & !_LC036 & !_LC038 & !_LC049 &
!_LC057 & !_LC062 & _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!AS3 & BS3);
_X002 = EXP( AS3 & !BS3);
_X003 = EXP(!AS2 & BS2);
_X004 = EXP( AS2 & !BS2);
-- Node name is '~143~1'
-- Equation name is '~143~1', location is LC062, type is buried.
-- synthesized logic cell
_LC062 = LCELL( _EQ003 $ GND);
_EQ003 = AH102 & !BH102
# !AH102 & BH102
# AH103 & !BH103
# !AH103 & BH103
# AH0 & !BH0;
-- Node name is '~143~2'
-- Equation name is '~143~2', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ004 $ GND);
_EQ004 = !AH0 & BH0
# AH1 & !BH1
# !AH1 & BH1
# AH2 & !BH2
# !AH2 & BH2;
-- Node name is '~143~3'
-- Equation name is '~143~3', location is LC049, type is buried.
-- synthesized logic cell
_LC049 = LCELL( _EQ005 $ GND);
_EQ005 = AH3 & !BH3
# !AH3 & BH3
# AM100 & !BM100
# !AM100 & BM100
# AM101 & !BM101;
-- Node name is '~143~4'
-- Equation name is '~143~4', location is LC001, type is buried.
-- synthesized logic cell
_LC001 = LCELL( _EQ006 $ GND);
_EQ006 = !AM101 & BM101
# AM102 & !BM102
# !AM102 & BM102
# AM103 & !BM103
# !AM103 & BM103;
-- Node name is '~143~5'
-- Equation name is '~143~5', location is LC033, type is buried.
-- synthesized logic cell
_LC033 = LCELL( _EQ007 $ GND);
_EQ007 = AM0 & !BM0
# !AM0 & BM0
# AM1 & !BM1
# !AM1 & BM1
# AM2 & !BM2;
-- Node name is '~143~6'
-- Equation name is '~143~6', location is LC035, type is buried.
-- synthesized logic cell
_LC035 = LCELL( _EQ008 $ GND);
_EQ008 = !AM2 & BM2
# AM3 & !BM3
# !AM3 & BM3
# AS100 & !BS100
# !AS100 & BS100;
-- Node name is '~143~7'
-- Equation name is '~143~7', location is LC036, type is buried.
-- synthesized logic cell
_LC036 = LCELL( _EQ009 $ GND);
_EQ009 = AS101 & !BS101
# !AS101 & BS101
# AS102 & !BS102
# !AS102 & BS102
# AS103 & !BS103;
-- Node name is '~143~8'
-- Equation name is '~143~8', location is LC038, type is buried.
-- synthesized logic cell
_LC038 = LCELL( _EQ010 $ GND);
_EQ010 = !AS103 & BS103
# AS0 & !BS0
# !AS0 & BS0
# AS1 & !BS1
# !AS1 & BS1;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\gongzuo\digital clock\comp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,424K
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