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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "chooser.v"ERROR:HDLCompilers:207 - "chooser.v" line 22 Signal 'ab' is not referenced in the module port listERROR:HDLCompilers:26 - "chooser.v" line 22 expecting ';', found ','ERROR:HDLCompilers:28 - "chooser.v" line 28 'a' has not been declaredERROR:HDLCompilers:28 - "chooser.v" line 28 'b' has not been declaredERROR:HDLCompilers:26 - "chooser.v" line 31 Macro reference `d0 is not definedAnalysis of file <"chooser.prj"> failed.--> Total memory usage is 77048 kilobytesNumber of errors : 5 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "chooser.v"ERROR:HDLCompilers:26 - "chooser.v" line 22 expecting ';', found ','ERROR:HDLCompilers:26 - "chooser.v" line 31 Macro reference `d0 is not definedAnalysis of file <"chooser.prj"> failed.--> Total memory usage is 77048 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "chooser.v"ERROR:HDLCompilers:26 - "chooser.v" line 31 Macro reference `d0 is not definedAnalysis of file <"chooser.prj"> failed.--> Total memory usage is 77048 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "chooser.v"ERROR:HDLCompilers:26 - "chooser.v" line 32 Macro reference `d1 is not definedAnalysis of file <"chooser.prj"> failed.--> Total memory usage is 77048 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "chooser.v"Module <chooser> compiledNo errors in compilationAnalysis of file <"chooser.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <chooser>.Module <chooser> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <chooser>. Related source file is "chooser.v". Found 4-bit 8-to-1 multiplexer for signal <out>. Summary: inferred 4 Multiplexer(s).Unit <chooser> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Multiplexers : 1 4-bit 8-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <chooser> ...Loading device for application Rf_Device from file 'v100.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block chooser, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-5 Number of Slices: 8 out of 1200 0% Number of 4 input LUTs: 16 out of 2400 0% Number of bonded IOBs: 39 out of 170 22% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 11.466ns=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Compiling verilog file "chooser.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
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