chooser_test.v

chooser the one form two

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:10:25 10/08/2008
// Design Name:   chooser
// Module Name:   chooser_test.v
// Project Name:  chooser
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: chooser
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module chooser_test_v;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;
	reg [3:0] c;
	reg [3:0] d;
	reg [3:0] e;
	reg [3:0] f;
	reg [3:0] g;
	reg [3:0] h;
	reg [2:0] choose;

	// Outputs
	wire [3:0] out;

	// Instantiate the Unit Under Test (UUT)
	chooser uut (
		.a(a), 
		.b(b), 
		.c(c), 
		.d(d), 
		.e(e), 
		.f(f), 
		.g(g), 
		.h(h), 
		.choose(choose), 
		.out(out)
	);

	initial begin
		// Initialize Inputs
		a = {$random}%16; //Give a radom number blongs to [0,15] .
		b = {$random}%16; //Give a radom number blongs to [0,15].
		c = {$random}%16; //Give a radom number blongs to [0,15] .
		d = {$random}%16; //Give a radom number blongs to [0,15] .
		e = {$random}%16; //Give a radom number blongs to [0,15] .
		f = {$random}%16; //Give a radom number blongs to [0,15] .
		g = {$random}%16; //Give a radom number blongs to [0,15] .
		h = {$random}%16; //Give a radom number blongs to [0,15] .
		choose = 0;

		// Wait 100 ns for global reset to finish
		
		#100;	choose=0;
		#100;	choose=1;
		#100;	choose=2;
		#100;	choose=3;
		#100;	choose=4;
		#100;	choose=5;
		#100;	choose=6;
		#100;	choose=7;
		#100;	a=4'b0011;
		#1000; $stop;


        
		// Add stimulus here

	end
      
endmodule