cymometer_register_file.v

nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			cymometer_register_file.v
** Last modified Date:	2006-02-23
** Last Version:		1.0
** Descriptions:		cymometer register define
**------------------------------------------------------------------------------------------------------
** Created by:			Zhou Shuwu
** Created date:		2006-02-23
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module cymometer_register_file(	
	//Avalon Signals
	clock,
	reset_n, 
	chip_select,
	address,
	write,
	write_data,
	freq_result,  //
	read,
	
	read_data,
	clock_divide
);
	
		input 			clock;			    //System Clock
		input 			reset_n;			//System Reset
		input 			chip_select;		//Avalon Chip select signal
		input[1:0]	 	address;	     	//Avalon Address bus 
		input 			write;				//Avalon Write signal
		input[31:0] 	write_data;			//Avalon Write data bus
		input[31:0]		freq_result;
		input			read;				//Avalon read signal
		
		output[31:0]	read_data;			//Avalon read data bus
		output[31:0] 	clock_divide; //cymometer clock divide drive signals

//Signal Declarations	
reg [31:0] 	clock_divide_r;		//Clock divider register
reg [31:0]	read_data_r;        //read data Register  

wire		write_act;
wire		read_act;

//determine if a vaild transaction was initiated 
assign write_act = chip_select & write;		
assign read_act  = chip_select & read;

//Parameters
//define the clock_divide_reg initial value
parameter clock_divide_reg_init = 32'd48_000_000;

//define the cymometer device's registers offset address 
parameter clock_divide_reg		= 2'h0,   //read and write enable 
		  freq_result_reg		= 2'h1;   //only read enable

//write
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)
	begin
		//initializtion
		clock_divide_r <= clock_divide_reg_init;
	end
	else if (write_act)     
	begin		
		case (address)
			clock_divide_reg:
			begin				
				clock_divide_r <= write_data;
			end
		default:
		begin
			clock_divide_r <= clock_divide_r;
		end
		endcase
	end
	else
	begin
		clock_divide_r <= clock_divide_r;
	end
end

//read
always @(read_act)
begin
	if (read_act)
	begin
		case (address)
				clock_divide_reg:
				begin
					read_data_r <= clock_divide_r;
				end
				freq_result_reg:
				begin
					read_data_r <= freq_result;
				end	
				default:
				begin
					read_data_r <= 32'h0;
				end
		endcase
	end
	else
		read_data_r <= 32'h0;
end

assign clock_divide = clock_divide_r;
assign read_data = read_data_r;

endmodule