addr_trans.v

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/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			addr_trans.v
** Last modified Date:	2005-12-13
** Last Version:		1.0
** Descriptions:		translate address code to digit enable code
**------------------------------------------------------------------------------------------------------
** Created by:			zhangjing
** Created date:		2006-2-14
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module addr_trans(
	addr,
	seven_segdisp_enable,
	digit_cs
	);
	input[2:0] 	addr;
	input 		seven_segdisp_enable;
	output[7:0] digit_cs;

	reg[7:0] 	digit_cs;

always@(addr or seven_segdisp_enable)
begin
  if(seven_segdisp_enable)
  begin
	case (addr)
		3'h0:
			begin
				digit_cs = 8'b1111_1110;
			end
		3'h1:
			begin
				digit_cs = 8'b1111_1101;
			end
		3'h2:
			begin
				digit_cs = 8'b1111_1011;
			end
		3'h3:
			begin
				digit_cs = 8'b1111_0111;
			end
		3'h4:
			begin
				digit_cs = 8'b1110_1111;
			end
		3'h5:
			begin
				digit_cs = 8'b1101_1111;
			end
		3'h6:
			begin
				digit_cs = 8'b1011_1111;
			end
		3'h7:
			begin
				digit_cs = 8'b0111_1111;
			end			
	endcase
  end
  else
  begin
     digit_cs = 8'b0111_1111;
  end
end
endmodule