tlc5620.v

nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验

//Legal Notice: (C)2005 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module tlc5620 (
                 // inputs:
                  address,
                  chip_select,
                  clock,
                  reset_n,
                  write,
                  write_data,

                 // outputs:
                  dac_clk,
                  dac_data,
                  dac_ldac,
                  dac_load
               );

  output           dac_clk;
  output           dac_data;
  output           dac_ldac;
  output           dac_load;
  input   [  1: 0] address;
  input            chip_select;
  input            clock;
  input            reset_n;
  input            write;
  input   [ 31: 0] write_data;

  wire             dac_clk;
  wire             dac_data;
  wire             dac_ldac;
  wire             dac_load;
  tlc5620_avalon_interface the_tlc5620_avalon_interface
    (
      .address     (address),
      .chip_select (chip_select),
      .clock       (clock),
      .dac_clk     (dac_clk),
      .dac_data    (dac_data),
      .dac_ldac    (dac_ldac),
      .dac_load    (dac_load),
      .reset_n     (reset_n),
      .write       (write),
      .write_data  (write_data)
    );



endmodule