smartsopc_standard_1c6.tan.rpt

nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                                                                                 ; To                                                                                                                                    ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 9.947 ns                                       ; UART_RXD                                                                                                                             ; niso2_1c6:inst|uart:the_uart|uart_rx:the_uart_rx|d1_source_rxd                                                                        ;                                          ; SYS_CLK2                                 ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 13.326 ns                                      ; niso2_1c6:inst|ext_bus_avalon_slave_arbitrator:the_ext_bus_avalon_slave|chipselect_n_to_the_lcd128_64                                ; LCD_EN                                                                                                                                ; SYS_CLK2                                 ;                                          ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 2.124 ns                                       ; altera_internal_jtag~TDO                                                                                                             ; altera_reserved_tdo                                                                                                                   ;                                          ;                                          ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; 4.358 ns                                       ; altera_internal_jtag                                                                                                                 ; niso2_1c6:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7]                                         ;                                          ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'pll:inst21|altpll:altpll_component|_clk0' ; 2.981 ns  ; 48.00 MHz ( period = 20.833 ns ) ; 56.02 MHz ( period = 17.852 ns )               ; niso2_1c6:inst|cpu:the_cpu|i_read                                                                                                    ; niso2_1c6:inst|ext_bus_avalon_slave_arbitrator:the_ext_bus_avalon_slave|ext_bus_address[16]                                           ; pll:inst21|altpll:altpll_component|_clk0 ; pll:inst21|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'SYS_CLK2'                                 ; 16.060 ns ; 48.00 MHz ( period = 20.833 ns ) ; 209.51 MHz ( period = 4.773 ns )               ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                      ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                       ; SYS_CLK2                                 ; SYS_CLK2                                 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'             ; N/A       ; None                             ; 98.95 MHz ( period = 10.106 ns )               ; sld_hub:sld_hub_inst|jtag_debug_mode                                                                                                 ; niso2_1c6:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate                                          ; altera_internal_jtag~TCKUTAP             ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'FREQ_INPUT'                               ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; niso2_1c6:inst|cymometer:the_cymometer|cymometer_avalon_interface:the_cymometer_avalon_interface|cymometer_task_logic:U1|pre_freq[2] ; niso2_1c6:inst|cymometer:the_cymometer|cymometer_avalon_interface:the_cymometer_avalon_interface|cymometer_task_logic:U1|pre_freq[31] ; FREQ_INPUT                               ; FREQ_INPUT                               ; 0            ;
; Clock Hold: 'pll:inst21|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                                            ; niso2_1c6:inst|jtag_uart:the_jtag_uart|av_waitrequest                                                                                ; niso2_1c6:inst|jtag_uart:the_jtag_uart|av_waitrequest                                                                                 ; pll:inst21|altpll:altpll_component|_clk0 ; pll:inst21|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYS_CLK2'                                  ; 1.314 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                                            ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[9]                      ; delay_reset_block:inst20|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[9]                       ; SYS_CLK2                                 ; SYS_CLK2                                 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                                ;                                                                                                                                      ;                                                                                                                                       ;                                          ;                                          ; 0            ;
+---------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;