smartsopc_standard_1c6.tan.rpt

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Timing Analyzer report for SmartSOPC_standard_1c6
Wed Aug 16 17:09:22 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'pll:inst21|altpll:altpll_component|_clk0'
  6. Clock Setup: 'SYS_CLK2'
  7. Clock Setup: 'altera_internal_jtag~TCKUTAP'
  8. Clock Setup: 'FREQ_INPUT'
  9. Clock Hold: 'pll:inst21|altpll:altpll_component|_clk0'
 10. Clock Hold: 'SYS_CLK2'
 11. tsu
 12. tco
 13. tpd
 14. th
 15. Timing Analyzer Messages



----------------
; Legal Notice ;
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Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.