tlc5620_task_logic.v

nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			tlc5620_task_logic.v
** Last modified Date:	2005-12-14
** Last Version:		1.0
** Descriptions:		tlc5620 logic
**------------------------------------------------------------------------------------------------------
** Created by:			ZhouShuwu
** Created date:		2005-12-14
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module tlc5620_task_logic(
	clock,
	reset_n,
	
	clock_divide,
	write_data,
	write_act,

	dac_clk,
	dac_data,
	dac_load,
	dac_ldac
	);

	//Inputs
	input clock;				//Input system clock to be divided
	input reset_n;				//Reset
	
	input [31:0]  clock_divide;	//Clock Divider value
	input [10:0]  write_data;   //DAC 11bit data 
    						  	//bit[10:9] is for channel selection
								//      00: channel DACA, 01: channel DACB, 
								//      10: channel DACC, 11: channel DACD
								//bit[8]    is RNG bit.it controls the DAC output range.
								//      0 : the output range is between the applied reference voltage and GND
								//      1 : the output range is between the twice the applied reference voltage and GND
								//bit[7:0]  is the DAC CODE for convertion. The CODE value is in the range 0 to 255.
								//	        Vo=REF*(CODE/256)*(1+RNG bit value)igital data to convert to agalog
	input		  write_act;  	//the signal of writing 11bits data to write_data
		
	//Outputs
	output dac_clk;             //DAC clk output
	output dac_data;			//DAC data output
	output dac_load;            //DAC load output
	output dac_ldac;            //DAC ldac output

//Signal Declarations	

reg [31:0] 	counter;		    //DAC Internal Counter

reg			dac_clk_r;          //DAC clk output register = clock/(2*clock_divide)
reg 		dac_data_r;		    //DAC data output register
reg 		dac_load_r;         //DAC load output register

reg [4:0] 	bit_counter;        //DAC data output bit counter
reg 		div_clk;            //the divider clock = clock/clock_divide 
reg 		bit_counter_rst;    //bit_counter reset
reg [1:0]	dac_sta,dac_sta_next;
wire		dac_dat_send_finish;


//**********************************************************
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)           
	begin
		counter <= 32'h0;
	end
	else
	begin
		if (counter < clock_divide)
 	    begin
 	    	counter <= counter + 32'h1;
 	    	div_clk <= 1'h0;
 	    end
 	    else
 	    begin
 	    	counter <= 32'h0;
 	    	div_clk <= 1'h1;
 	    end
 	end
end


//**********************************************************

//**********************************************************
parameter		dac_idle 	= 2'h0,
				dac_send 	= 2'h1,
				dac_store 	= 2'h2;
			
//状态机
always @(posedge clock or negedge reset_n)
begin
	if (~reset_n)
		dac_sta <= dac_idle;
	else
		dac_sta <= dac_sta_next;
end

//状态描述
always @(dac_sta or write_act or div_clk or dac_dat_send_finish)
begin
	dac_load_r <= 1'b1;
	bit_counter_rst <= 1'b0;
	dac_sta_next <= dac_idle;
	case(dac_sta)
		dac_idle:
		begin
			bit_counter_rst <= 1'b1;  //空闲时复位发送位计数器
			if (write_act)            //有写数据信号时,进入发送状态
				dac_sta_next <= dac_send;
			else
				dac_sta_next <= dac_idle;
		end
		
		dac_send:
		begin
			if (dac_dat_send_finish)  //位数据发送完成后进入数据锁存状态
				dac_sta_next <= dac_store;
			else
				dac_sta_next <= dac_send;
		end
		
		dac_store:
		begin
			bit_counter_rst <= 1'b1; //发送位计数器复位
			dac_load_r <= 1'b0;      //Load 变低进行数据锁存
			if (div_clk)             //锁存状态为1个div_clk周期
				dac_sta_next <= dac_idle;
			else
				dac_sta_next <= dac_store;
		end
		
	endcase
end
//**********************************************************

//**********************************************************

always @(posedge clock)
begin
	if (bit_counter_rst)
	begin
		bit_counter <= 5'h0; //发送位计数器清0
	end
	else if (div_clk)        //发送位计数器累加
	begin
		bit_counter <= bit_counter + 5'h1;
    end
end

//当发送位计数器计数到24时，发送完毕
assign dac_dat_send_finish = (bit_counter == 5'd24);

always @(bit_counter[4:1] or write_data)
begin
	case (bit_counter[4:1]) //发送计数器第[4:1]位变换时,发送1bit数据
		4'd1 :	dac_data_r <= write_data[10];//先高位
		4'd2 :	dac_data_r <= write_data[9];
		4'd3 :	dac_data_r <= write_data[8];
		4'd4 :	dac_data_r <= write_data[7];
		4'd5 :	dac_data_r <= write_data[6];
		4'd6 :	dac_data_r <= write_data[5];
		4'd7 :	dac_data_r <= write_data[4];
		4'd8 :	dac_data_r <= write_data[3];
		4'd9 :	dac_data_r <= write_data[2];
		4'd10:	dac_data_r <= write_data[1];
		4'd11:	dac_data_r <= write_data[0];
		default:dac_data_r <= 1'b1;
	endcase
end

//在发送位计数器2－24间产生dac clk
always @(bit_counter)
begin
	if ((bit_counter < 5'd24) & (bit_counter >= 5'd2))
	begin
		dac_clk_r <= ~bit_counter[0];
	end
	else
		dac_clk_r <= 1'b0;
end


assign dac_clk  = dac_clk_r;
assign dac_data = dac_data_r;
assign dac_load = dac_load_r;
assign dac_ldac = 1'b0;

//**********************************************************

endmodule