seven_segdisp.v

来自「nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验」· Verilog 代码 · 共 64 行

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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module seven_segdisp (
                       // inputs:
                        address,
                        chip_select,
                        clock,
                        read,
                        reset_n,
                        write,
                        write_data,

                       // outputs:
                        digit_cs,
                        read_data,
                        seg_code
                     );

  output  [  7: 0] digit_cs;
  output  [ 31: 0] read_data;
  output  [  7: 0] seg_code;
  input   [  3: 0] address;
  input            chip_select;
  input            clock;
  input            read;
  input            reset_n;
  input            write;
  input   [ 31: 0] write_data;

  wire    [  7: 0] digit_cs;
  wire    [ 31: 0] read_data;
  wire    [  7: 0] seg_code;
  seven_segdisp_avalon_interface the_seven_segdisp_avalon_interface
    (
      .address     (address),
      .chip_select (chip_select),
      .clock       (clock),
      .digit_cs    (digit_cs),
      .read        (read),
      .read_data   (read_data),
      .reset_n     (reset_n),
      .seg_code    (seg_code),
      .write       (write),
      .write_data  (write_data)
    );



endmodule