irclk_pwm.v

nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验

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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
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//agreement for further details.

// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module irclk_pwm (
                   // inputs:
                    address,
                    chip_select,
                    clock,
                    read,
                    reset_n,
                    write,
                    write_data,

                   // outputs:
                    pwm_out,
                    read_data
                 );

  output           pwm_out;
  output  [ 31: 0] read_data;
  input   [  1: 0] address;
  input            chip_select;
  input            clock;
  input            read;
  input            reset_n;
  input            write;
  input   [ 31: 0] write_data;

  wire             pwm_out;
  wire    [ 31: 0] read_data;
  pwm_avalon_interface the_pwm_avalon_interface
    (
      .address     (address),
      .chip_select (chip_select),
      .clock       (clock),
      .pwm_out     (pwm_out),
      .read        (read),
      .read_data   (read_data),
      .reset_n     (reset_n),
      .write       (write),
      .write_data  (write_data)
    );



endmodule