smartsopc_flash_programmer.map.rpt

来自「nios 嵌入式系统基础教程实验 创建目标板FLASH编程」· RPT 代码 · 共 320 行 · 第 1/5 页

Analysis & Synthesis report for SmartSOPC_Flash_Programmer
Sat Apr 29 16:03:11 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |SmartSOPC_Flash_Programmer_top|SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|a_fffifo:subfifo|a_fefifo:fifo_state|sm_emptyfull
  9. State Machine - |SmartSOPC_Flash_Programmer_top|SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|a_fffifo:subfifo|a_fefifo:fifo_state|sm_emptyfull
 10. Registers Protected by SYN_PRESERVE, DONT_TOUCH
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
 15. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
 16. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
 17. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
 18. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
 19. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram
 20. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
 21. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
 22. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
 23. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
 24. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram
 25. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram
 26. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
 27. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
 28. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
 29. Parameter Settings for User Entity Instance: SmartSOPC_Flash_Programmer:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram
 30. Parameter Settings for User Entity Instance: SYS_CLK:inst1|altpll:altpll_component
 31. Parameter Settings for User Entity Instance: delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
 32. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 33. scfifo Parameter Settings by Entity Instance
 34. Analysis & Synthesis Equations
 35. Analysis & Synthesis Messages



----------------
; Legal Notice ;
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Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.