smartsopc_flash_programmer.tan.qmsg

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode register SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 102.73 MHz 9.734 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 102.73 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode\" and destination register \"SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate\" (period= 9.734 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.606 ns + Longest register register " "Info: + Longest register to register delay is 4.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode 1 REG LC_X7_Y6_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N0; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.275 ns) + CELL(0.590 ns) 1.865 ns SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~48 2 COMB LC_X7_Y5_N5 4 " "Info: 2: + IC(1.275 ns) + CELL(0.590 ns) = 1.865 ns; Loc. = LC_X7_Y5_N5; Fanout = 4; COMB Node = 'SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~48'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "1.865 ns" { sld_hub:sld_hub_inst|jtag_debug_mode SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.292 ns) 3.283 ns SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0 3 COMB LC_X9_Y5_N4 1 " "Info: 3: + IC(1.126 ns) + CELL(0.292 ns) = 3.283 ns; Loc. = LC_X9_Y5_N4; Fanout = 1; COMB Node = 'SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "1.418 ns" { SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.867 ns) 4.606 ns SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 4 REG LC_X9_Y5_N2 2 " "Info: 4: + IC(0.456 ns) + CELL(0.867 ns) = 4.606 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; REG Node = 'SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "1.323 ns" { SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.749 ns 37.97 % " "Info: Total cell delay = 1.749 ns ( 37.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.857 ns 62.03 % " "Info: Total interconnect delay = 2.857 ns ( 62.03 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "4.606 ns" { sld_hub:sld_hub_inst|jtag_debug_mode SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.606 ns" { sld_hub:sld_hub_inst|jtag_debug_mode SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 1.275ns 1.126ns 0.456ns } { 0.000ns 0.590ns 0.292ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 96 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 96; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 2 REG LC_X9_Y5_N2 2 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; REG Node = 'SmartSOPC_Flash_Programmer:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.292 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 96 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 96; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|jtag_debug_mode 2 REG LC_X7_Y6_N0 2 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X7_Y6_N0; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 382 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "4.606 ns" { sld_hub:sld_hub_inst|jtag_debug_mode SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.606 ns" { sld_hub:sld_hub_inst|jtag_debug_mode SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 1.275ns 1.126ns 0.456ns } { 0.000ns 0.590ns 0.292ns 0.867ns } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "SYS_CLK:inst1\|altpll:altpll_component\|_clk0 register SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\] register SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\] 822 ps " "Info: Minimum slack time is 822 ps for clock \"SYS_CLK:inst1\|altpll:altpll_component\|_clk0\" between source register \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\]\" and destination register \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns + Shortest register register " "Info: + Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\] 1 REG LC_X27_Y12_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y12_N0; Fanout = 4; REG Node = 'SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\]'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1890 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\] 2 REG LC_X27_Y12_N0 4 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X27_Y12_N0; Fanout = 4; REG Node = 'SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\]'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "0.613 ns" { SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1890 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.613 ns 100.00 % " "Info: Total cell delay = 0.613 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "0.613 ns" { SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.613 ns" { SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } { 0.0ns 0.0ns } { 0.0ns 0.613ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SYS_CLK:inst1\|altpll:altpll_component\|_clk0 12.499 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"SYS_CLK:inst1\|altpll:altpll_component\|_clk0\" is 12.499 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SYS_CLK:inst1\|altpll:altpll_component\|_clk0 12.499 ns -1.885 ns  50 " "Info: Clock period of Source clock \"SYS_CLK:inst1\|altpll:altpll_component\|_clk0\" is 12.499 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK:inst1\|altpll:altpll_component\|_clk0 destination 2.385 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SYS_CLK:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2832 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2832; CLK Node = 'SYS_CLK:inst1\|altpll:altpll_component\|_clk0'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { SYS_CLK:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\] 2 REG LC_X27_Y12_N0 4 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X27_Y12_N0; Fanout = 4; REG Node = 'SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\]'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1890 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 29.81 % " "Info: Total cell delay = 0.711 ns ( 29.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns 70.19 % " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } { 0.0ns 1.674ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK:inst1\|altpll:altpll_component\|_clk0 source 2.385 ns - Shortest register " "Info: - Shortest clock path from clock \"SYS_CLK:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SYS_CLK:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 2832 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 2832; CLK Node = 'SYS_CLK:inst1\|altpll:altpll_component\|_clk0'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { SYS_CLK:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.711 ns) 2.385 ns SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\] 2 REG LC_X27_Y12_N0 4 " "Info: 2: + IC(1.674 ns) + CELL(0.711 ns) = 2.385 ns; Loc. = LC_X27_Y12_N0; Fanout = 4; REG Node = 'SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_fill_dp_offset\[1\]'" {  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1890 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 29.81 % " "Info: Total cell delay = 0.711 ns ( 29.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns 70.19 % " "Info: Total interconnect delay = 1.674 ns ( 70.19 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } { 0.0ns 1.674ns } { 0.0ns 0.711ns } } }  } 0}  } { { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.385 ns" { SYS_CLK:inst1|altpll:altpll_component|_clk0 SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1] } { 0.0ns 1.674ns } { 0.0ns 0.711ns } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "2.385 ns" { SYS_CLK:inst1|altpll:alt