smartsopc_flash_programmer.map.qmsg

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(596) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(596): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 596 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(614) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(614): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 614 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_instruction_master_arbitrator SmartSOPC_Flash_Programmer:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master " "Info: Elaborating entity \"cpu_0_instruction_master_arbitrator\" for hierarchy \"SmartSOPC_Flash_Programmer:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master\"" {  } { { "SmartSOPC_Flash_Programmer.v" "the_cpu_0_instruction_master" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 3650 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "active_and_waiting_last_time SmartSOPC_Flash_Programmer.v(705) " "Info: (10035) Verilog HDL or VHDL information at SmartSOPC_Flash_Programmer.v(705): object \"active_and_waiting_last_time\" declared but not used" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 705 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_address_last_time SmartSOPC_Flash_Programmer.v(706) " "Info: (10035) Verilog HDL or VHDL information at SmartSOPC_Flash_Programmer.v(706): object \"cpu_0_instruction_master_address_last_time\" declared but not used" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 706 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_read_last_time SmartSOPC_Flash_Programmer.v(716) " "Info: (10035) Verilog HDL or VHDL information at SmartSOPC_Flash_Programmer.v(716): object \"cpu_0_instruction_master_read_last_time\" declared but not used" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 716 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 SmartSOPC_Flash_Programmer.v(736) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(736): truncated value with size 32 to match size of target (1)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 736 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 SmartSOPC_Flash_Programmer.v(742) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(742): truncated value with size 32 to match size of target (1)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 742 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 1 SmartSOPC_Flash_Programmer.v(750) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(750): truncated value with size 24 to match size of target (1)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 750 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 SmartSOPC_Flash_Programmer.v(772) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(772): truncated value with size 32 to match size of target (1)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 772 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "SmartSOPC_Flash_Programmer.v(773) " "Warning: (10037) Verilog HDL or VHDL warning at SmartSOPC_Flash_Programmer.v(773): condition expression evaluates to a constant" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 773 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(815) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(815): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 815 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "SmartSOPC_Flash_Programmer.v(816) " "Warning: (10037) Verilog HDL or VHDL warning at SmartSOPC_Flash_Programmer.v(816): condition expression evaluates to a constant" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 816 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(822) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(822): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 822 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(827) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(827): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 827 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 SmartSOPC_Flash_Programmer.v(840) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(840): truncated value with size 32 to match size of target (16)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 840 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(847) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(847): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 847 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(864) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(864): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 864 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(874) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(874): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 874 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SmartSOPC_Flash_Programmer.v(885) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(885): truncated value with size 32 to match size of target (2)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 885 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 SmartSOPC_Flash_Programmer.v(895) " "Warning: Verilog HDL assignment warning at SmartSOPC_Flash_Programmer.v(895): truncated value with size 32 to match size of target (1)" {  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 895 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_0.v 6 6 " "Info: Using design file cpu_0.v, which is not specified as a design file for the current project, but contains definitions for 6 design units and 6 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_ic_data_module " "Info: Found entity 1: cpu_0_ic_data_module" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_ic_tag_module " "Info: Found entity 2: cpu_0_ic_tag_module" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 113 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_bht_module " "Info: Found entity 3: cpu_0_bht_module" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 212 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 cpu_0_register_bank_a_module " "Info: Found entity 4: cpu_0_register_bank_a_module" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 311 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_0_register_bank_b_module " "Info: Found entity 5: cpu_0_register_bank_b_module" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 410 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_0 " "Info: Found entity 6: cpu_0" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 509 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0 SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0 " "Info: Elaborating entity \"cpu_0\" for hierarchy \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\"" {  } { { "SmartSOPC_Flash_Programmer.v" "the_cpu_0" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 3669 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_0_test_bench.v 1 1 " "Info: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_test_bench " "Info: Found entity 1: cpu_0_test_bench" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_test_bench SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench " "Info: Elaborating entity \"cpu_0_test_bench\" for hierarchy \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench\"" {  } { { "cpu_0.v" "the_cpu_0_test_bench" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1952 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_0_is_x cpu_0_test_bench.v(95) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(95): object \"A_wr_data_unfiltered_0_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 95 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_10_is_x cpu_0_test_bench.v(96) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(96): object \"A_wr_data_unfiltered_10_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 96 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_11_is_x cpu_0_test_bench.v(97) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(97): object \"A_wr_data_unfiltered_11_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 97 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_12_is_x cpu_0_test_bench.v(98) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(98): object \"A_wr_data_unfiltered_12_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 98 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_13_is_x cpu_0_test_bench.v(99) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(99): object \"A_wr_data_unfiltered_13_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 99 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_14_is_x cpu_0_test_bench.v(100) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(100): object \"A_wr_data_unfiltered_14_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 100 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_15_is_x cpu_0_test_bench.v(101) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(101): object \"A_wr_data_unfiltered_15_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 101 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_16_is_x cpu_0_test_bench.v(102) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(102): object \"A_wr_data_unfiltered_16_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 102 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_17_is_x cpu_0_test_bench.v(103) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(103): object \"A_wr_data_unfiltered_17_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 103 0 0 } }  } 0}