smartsopc_flash_programmer.fit.qmsg

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_CANT_PACK_FAST_REGISTER_IO" "A\[0\] " "Warning: Can't pack node A\[0\] to I/O pin" { { "Warning" "WFSAC_FSAC_REGISTER_PACKING_NO_OUTPUT_IO_REGISTER_CONNECTION" "A\[0\] " "Warning: Can't pack node A\[0\] -- no packable connection between output pin and register" {  } { { "SmartSOPC_Flash_Programmer_top.bdf" "" { Schematic "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer_top.bdf" { { 120 1000 1176 136 "A\[20..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { A[0] } "NODE_NAME" } "" } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" "" { A[0] } "NODE_NAME" } }  } 0}  } { { "SmartSOPC_Flash_Programmer_top.bdf" "" { Schematic "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer_top.bdf" { { 120 1000 1176 136 "A\[20..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { A[0] } "NODE_NAME" } "" } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" "" { A[0] } "NODE_NAME" } }  } 2}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[21\] " "Warning: Node \"A\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[21\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "A\[22\] " "Warning: Node \"A\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[22\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FLASH_RnB " "Warning: Node \"FLASH_RnB\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_RnB" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FLASH_nCS2 " "Warning: Node \"FLASH_nCS2\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_nCS2" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SYS_CLK0 " "Warning: Node \"SYS_CLK0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SYS_CLK0" } } } }  } 0}  } {  } 0}