smartsopc_flash_programmer.fit.qmsg

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "SYS_CLK:inst1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"SYS_CLK:inst1\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SYS_CLK:inst1\|altpll:altpll_component\|_clk0" } { 0 "SYS_CLK:inst1\|altpll:altpll_component\|_clk0" } } } } { "SmartSOPC_Flash_Programmer_top.bdf" "" { Schematic "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer_top.bdf" { { -112 472 712 48 "inst1" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { SYS_CLK:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" "" { SYS_CLK:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" "" { Report "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer_cmp.qrpt" Compiler "SmartSOPC_Flash_Programmer" "UNKNOWN" "V1" "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/db/SmartSOPC_Flash_Programmer.quartus_db" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" { Floorplan "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "SYS_nRST Global clock in PIN 29 " "Info: Automatically promoted some destinations of signal \"SYS_nRST\" to use Global clock in PIN 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "delay_reset_block:inst3\|inst4 " "Info: Destination \"delay_reset_block:inst3\|inst4\" may be non-global or may not use global clock" {  } { { "delay_reset_block.bdf" "" { Schematic "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0}  } { { "SmartSOPC_Flash_Programmer_top.bdf" "" { Schematic "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer_top.bdf" { { 112 336 504 128 "SYS_nRST" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "SmartSOPC_Flash_Programmer:inst\|SmartSOPC_Flash_Programmer_reset_clk_domain_synch_module:SmartSOPC_Flash_Programmer_reset_clk_domain_synch\|data_out Global clock " "Info: Automatically promoted some destinations of signal \"SmartSOPC_Flash_Programmer:inst\|SmartSOPC_Flash_Programmer_reset_clk_domain_synch_module:SmartSOPC_Flash_Programmer_reset_clk_domain_synch\|data_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wren " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wren\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1903 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[0\]~449 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[0\]~449\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1900 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[1\]~450 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[1\]~450\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1900 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[2\]~451 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[2\]~451\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1900 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[3\]~452 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[3\]~452\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1900 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[5\]~184 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[5\]~184\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1901 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[6\]~185 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[6\]~185\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1901 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[4\]~186 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[4\]~186\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1901 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[7\]~187 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[7\]~187\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1901 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[2\]~188 " "Info: Destination \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|ic_tag_wrdata\[2\]~188\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 1901 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "SmartSOPC_Flash_Programmer.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/SmartSOPC_Flash_Programmer.v" 3294 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0\" to use Global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|clear_signal Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|clear_signal\" to use Global clock" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "delay_reset_block:inst3\|inst4 Global clock " "Info: Automatically promoted signal \"delay_reset_block:inst3\|inst4\" to use Global clock" {  } { { "delay_reset_block.bdf" "" { Schematic "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0}