smartsopc_flash_programmer.tan.rpt

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                             ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; SYS_CLK:inst1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 80.01 MHz        ; 0.000 ns      ; 0.000 ns     ; SYS_CLK1 ; 5                     ; 3                   ; -1.885 ns ;              ;
; SYS_CLK1                                    ;                    ; User Pin   ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP                ;                    ; User Pin   ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SYS_CLK:inst1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                         ; To                                                                                                                                                                   ; From Clock                                  ; To Clock                                    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 0.745 ns                                ; 85.08 MHz ( period = 11.754 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|D_iw[4]                                                                                                                                      ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_regnum_a_cmp_D                                                                                                     ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.206 ns                 ; 11.461 ns               ;
; 0.935 ns                                ; 86.48 MHz ( period = 11.564 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|D_iw[4]                                                                                                                                      ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_regnum_b_cmp_D                                                                                                     ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.206 ns                 ; 11.271 ns               ;
; 0.939 ns                                ; 86.51 MHz ( period = 11.560 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|A_mem_baddr[23]                                                                                                                              ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|A_slow_inst_result[21]                                                                                               ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.187 ns                 ; 11.248 ns               ;
; 0.970 ns                                ; 86.74 MHz ( period = 11.529 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_logic_op[0]                                                                                                                                ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_src2_reg[0]                                                                                                        ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.238 ns                 ; 11.268 ns               ;
; 0.987 ns                                ; 86.87 MHz ( period = 11.512 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_logic_op[1]                                                                                                                                ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_src2_reg[0]                                                                                                        ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.238 ns                 ; 11.251 ns               ;
; 1.083 ns                                ; 87.60 MHz ( period = 11.416 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|D_iw[5]                                                                                                                                      ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_regnum_a_cmp_D                                                                                                     ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.206 ns                 ; 11.123 ns               ;
; 1.085 ns                                ; 87.61 MHz ( period = 11.414 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_src2[5]                                                                                                                                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_src2_reg[0]                                                                                                        ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.238 ns                 ; 11.153 ns               ;
; 1.096 ns                                ; 87.70 MHz ( period = 11.403 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_src2[28]                                                                                                                                   ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_src2_reg[0]                                                                                                        ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.238 ns                 ; 11.142 ns               ;
; 1.128 ns                                ; 87.94 MHz ( period = 11.371 ns )                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|A_mem_baddr[19]                                                                                                                              ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|A_slow_inst_result[21]                                                                                               ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 12.499 ns                   ; 12.187 ns                 ; 11.059 ns               ;