smartsopc_flash_programmer.tan.rpt

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Type                                                       ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                    ; To                                                                                                                                                 ; From Clock                                  ; To Clock                                    ; Failed Paths ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Worst-case tsu                                             ; N/A      ; None                             ; 2.051 ns                         ; D[7]                                                                                                                                    ; SmartSOPC_Flash_Programmer:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[7] ;                                             ; SYS_CLK1                                    ; 0            ;
; Worst-case tco                                             ; N/A      ; None                             ; 2.721 ns                         ; SmartSOPC_Flash_Programmer:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn ; nOE                                                                                                                                                ; SYS_CLK1                                    ;                                             ; 0            ;
; Worst-case tpd                                             ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                ; altera_reserved_tdo                                                                                                                                ;                                             ;                                             ; 0            ;
; Worst-case th                                              ; N/A      ; None                             ; 4.327 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                            ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]                                                                            ;                                             ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Clock Setup: 'SYS_CLK:inst1|altpll:altpll_component|_clk0' ; 0.745 ns ; 80.01 MHz ( period = 12.499 ns ) ; 85.08 MHz ( period = 11.754 ns ) ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|D_iw[4]                                                                                 ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|E_regnum_a_cmp_D                                                                                   ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                ; N/A      ; None                             ; 102.73 MHz ( period = 9.734 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode                                                                                                    ; SmartSOPC_Flash_Programmer:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate                                ; altera_internal_jtag~TCKUTAP                ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Clock Hold: 'SYS_CLK:inst1|altpll:altpll_component|_clk0'  ; 0.822 ns ; 80.01 MHz ( period = 12.499 ns ) ; N/A                              ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1]                                                                    ; SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1]                                                                               ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                               ;          ;                                  ;                                  ;                                                                                                                                         ;                                                                                                                                                    ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;