📄 smartsopc_flash_programmer.ptf.bak
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direction = "input";
width = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
# Date_Modified = "--unknown--";
Clock_Source = "clk";
View
{
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
<br>Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
# max entries in write fifo
read_depth = "64";
# max entries in read fifo
write_threshold = "8";
# Chars remaining in write fifo to trigger irq
read_threshold = "8";
# Spaces in read fifo to trigger irq
read_char_stream = "";
# simulated character input stream.
showascii = "1";
# (re)set by $INO/enable during finish
read_le = "0";
# 1=>use_eab=off; 0=>use_eab=on
write_le = "0";
# 1=>use_eab=off; 0=>use_eab=on
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
# These signals are "of interest" and are added to the waveform window, etc.
# The name of the section (e.g. "a2" or "f") doesn't "mean" anything, except
# that the signals will be displayed in the waveform window in-order, as
# sorted by these otherwise-meaningless names.
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
# next brace matches DISPLAY
}
INTERACTIVE_IN drive
{
enable = "0";
# file descriptors are really just suffixes for perl
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
# next brace matches SIMULATION
}
# next brace matches MODULE_DEFAULTS
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "4.0";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x00040000";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
View
{
Settings_Summary = "System ID (at last Generate):<br> <b>B8D2CABB</b> (unique ID tag) <br> <b>40631D1E</b> (timestamp: Thu Mar 25, 2004 @9:55 AM)";
Is_Collapsed = "1";
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
value0 = "1686625497u";
value1 = "1079118575u";
}
}
MODULE asmi
{
class = "altera_avalon_asmi";
class_version = "2.1";
SLAVE asmi_control_port
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Nonvolatile_Storage = "1";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x00060000";
Is_Base_Locked = "1";
}
PORT_WIRING
{
PORT asmi_select
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT data_from_cpu
{
direction = "input";
type = "writedata";
width = "16";
}
PORT data_to_cpu
{
direction = "output";
type = "readdata";
width = "16";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
}
PORT endofpacket
{
direction = "output";
type = "endofpacket";
width = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
}
PORT mem_addr
{
direction = "input";
type = "address";
width = "3";
}
PORT read_n
{
direction = "input";
type = "read_n";
width = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_asmi";
flash_reference_designator = "U10";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "CYCLONE,CYCLONEII";
Fixed_Module_Name = "asmi";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
databits = "8";
targetclock = "20";
clockunits = "MHz";
clockmult = "1000000";
numslaves = "1";
ismaster = "1";
clockpolarity = "0";
clockphase = "0";
lsbfirst = "0";
extradelay = "1";
targetssdelay = "100";
delayunits = "us";
delaymult = "1e-006";
prefix = "asmi_";
CONSTANTS
{
CONSTANT na_asmi_64K
{
value = "0";
comment = "ASMI part is 64k bits";
}
CONSTANT na_asmi_1M
{
value = "0";
comment = "ASMI part is 1M bits";
}
CONSTANT na_asmi_4M
{
value = "1";
comment = "ASMI part is 4M bits";
}
}
clockunit = "kHz";
delayunit = "us";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/asmi.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE Board_System
{
class = "altera_user_board_setup";
class_version = "1.0";
SLAVE bogus_slave
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Component_Name = "SmartSOPC_Board";
JTAG_device_index = "1";
name1 = "";
slave1 = "";
offset1 = "";
length1 = "";
name2 = "";
slave2 = "";
offset2 = "";
length2 = "";
name3 = "";
slave3 = "";
offset3 = "";
length3 = "";
name4 = "";
slave4 = "";
offset4 = "";
length4 = "";
name5 = "";
slave5 = "";
offset5 = "";
length5 = "";
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "Board_System";
Is_Visible = "0";
View
{
Is_Collapsed = "1";
MESSAGES
{
}
}
}
}
}
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