smartsopc_flash_programmer.ptf.bak

nios 嵌入式系统基础教程实验 创建目标板FLASH编程

                  value = "1";
                  comment = "Support debug routines";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "1";
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
            Is_Enabled = "0";
         }
      }
      PORT_WIRING 
      {
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Divider";
               name = "common";
               radix = "";
            }
            SIGNAL aap
            {
               format = "Logic";
               name = "clk";
               radix = "hexadecimal";
            }
            SIGNAL aaq
            {
               format = "Logic";
               name = "reset_n";
               radix = "hexadecimal";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "F_pcb_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL aav
            {
               format = "Logic";
               name = "R_vinst";
               radix = "ascii";
            }
            SIGNAL aaw
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL aax
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL aay
            {
               format = "Logic";
               name = "F_valid";
               radix = "hexadecimal";
            }
            SIGNAL aaz
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "R_valid";
               radix = "hexadecimal";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "D_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "D_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abg
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL abh
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
         }
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
   }
   MODULE firmware_ROM
   {
      class = "altera_avalon_onchip_memory2";
      class_version = "4.0";
      iss_model_name = "altera_memory";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/firmware_ROM.v";
         Synthesis_Only_Files = "";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         allow_mram_sim_contents_only_file = "0";
         ram_block_type = "M4K";
         gui_ram_block_type = "Automatic";
         Writeable = "0";
         dual_port = "0";
         Size_Value = "3584";
         Size_Multiple = "1";
         contents_info = "";
      }
      SYSTEM_BUILDER_INFO 
      {
         Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM";
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "onchip_memory";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "10";
            }
            PORT byteenable
            {
               direction = "input";
               type = "byteenable";
               width = "4";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT debugaccess
            {
               direction = "input";
               type = "debugaccess";
               width = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "32";
            }
            PORT write
            {
               direction = "input";
               type = "write";
               width = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "32";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Address_Width = "10";
            Data_Width = "32";