proj.tan.qmsg

液晶模块输出VHDL程序 程序实现的功能是标准的16×2字符型液晶模块上显示字符串

{ "Info" "ITDB_FULL_TCO_RESULT" "clk LCD_D\[3\] lcd:inst\|state\[2\] 33.793 ns register " "Info: tco from clock \"clk\" to destination pin \"LCD_D\[3\]\" through register \"lcd:inst\|state\[2\]\" is 33.793 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.142 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 16.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 3.295 ns div16:inst2\|count\[3\] 3 REG LCFF_X25_Y2_N1 2 " "Info: 3: + IC(1.089 ns) + CELL(0.989 ns) = 3.295 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'div16:inst2\|count\[3\]'" {  } { {