proj.tan.qmsg

液晶模块输出VHDL程序 程序实现的功能是标准的16×2字符型液晶模块上显示字符串

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst\|clk_int lcd:inst\|clk_int clk 424 ps " "Info: Found hold time violation between source  pin or register \"lcd:inst\|clk_int\" and destination pin or register \"lcd:inst\|clk_int\" for clock \"clk\" (Hold time is 424 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.034 ns + Largest " "Info: + Largest clock skew is 1.034 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.879 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 3.295 ns div16:inst2\|count\[3\] 3 REG LCFF_X25_Y2_N1 2 " "Info: 3: + IC(1.089 ns) + CELL(0.989 ns) = 3.295 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { clk~clkctrl div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.000 ns) 4.273 ns div16:inst2\|count\[3\]~clkctrl 4 COMB CLKCTRL_G13 16 " "Info: 4: + IC(0.978 ns) + CELL(0.000 ns) = 4.273 ns; Loc. = CLKCTRL_G13; Fanout = 16; COMB Node = 'div16:inst2\|count\[3\]~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.978 ns" { div16:inst2|count[3] div16:inst2|count[3]~clkctrl } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 6.351 ns lcd:inst\|clkcnt\[13\] 5 REG LCFF_X24_Y3_N27 3 " "Info: 5: + IC(1.089 ns) + CELL(0.989 ns) = 6.351 ns; Loc. = LCFF_X24_Y3_N27; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[13\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.636 ns) 7.757 ns lcd:inst\|reduce_nor~376 6 COMB LCCOMB_X25_Y3_N30 1 " "Info: 6: + IC(0.770 ns) + CELL(0.636 ns) = 7.757 ns; Loc. = LCCOMB_X25_Y3_N30; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~376'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.406 ns" { lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.636 ns) 8.763 ns lcd:inst\|reduce_nor~380 7 COMB LCCOMB_X25_Y3_N22 7 " "Info: 7: + IC(0.370 ns) + CELL(0.636 ns) = 8.763 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.006 ns" { lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.989 ns) 10.092 ns lcd:inst\|clkdiv 8 REG LCFF_X25_Y3_N19 2 " "Info: 8: + IC(0.340 ns) + CELL(0.989 ns) = 10.092 ns; Loc. = LCFF_X25_Y3_N19; Fanout = 2; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.329 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.000 ns) 11.109 ns lcd:inst\|clkdiv~clkctrl 9 COMB CLKCTRL_G15 2 " "Info: 9: + IC(1.017 ns) + CELL(0.000 ns) = 11.109 ns; Loc. = CLKCTRL_G15; Fanout = 2; COMB Node = 'lcd:inst\|clkdiv~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.017 ns" { lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.679 ns) 12.879 ns lcd:inst\|clk_int 10 REG LCFF_X25_Y1_N13 2 " "Info: 10: + IC(1.091 ns) + CELL(0.679 ns) = 12.879 ns; Loc. = LCFF_X25_Y1_N13; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.770 ns" { lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.018 ns 46.73 % " "Info: Total cell delay = 6.018 ns ( 46.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.861 ns 53.27 % " "Info: Total interconnect delay = 6.861 ns ( 53.27 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "12.879 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.879 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } { 0.0ns 0.0ns 0.117ns 1.089ns 0.978ns 1.089ns 0.77ns 0.37ns 0.34ns 1.017ns 1.091ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.636ns 0.636ns 0.989ns 0.0ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.845 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 11.845 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 3.295 ns div16:inst2\|count\[3\] 3 REG LCFF_X25_Y2_N1 2 " "Info: 3: + IC(1.089 ns) + CELL(0.989 ns) = 3.295 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { clk~clkctrl div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.000 ns) 4.273 ns div16:inst2\|count\[3\]~clkctrl 4 COMB CLKCTRL_G13 16 " "Info: 4: + IC(0.978 ns) + CELL(0.000 ns) = 4.273 ns; Loc. = CLKCTRL_G13; Fanout = 16; COMB Node = 'div16:inst2\|count\[3\]~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.978 ns" { div16:inst2|count[3] div16:inst2|count[3]~clkctrl } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 6.351 ns lcd:inst\|clkcnt\[6\] 5 REG LCFF_X25_Y3_N9 3 " "Info: 5: + IC(1.089 ns) + CELL(0.989 ns) = 6.351 ns; Loc. = LCFF_X25_Y3_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[6\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.378 ns) 7.159 ns lcd:inst\|reduce_nor~378 6 COMB LCCOMB_X25_Y3_N28 1 " "Info: 6: + IC(0.430 ns) + CELL(0.378 ns) = 7.159 ns; Loc. = LCCOMB_X25_Y3_N28; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~378'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.808 ns" { lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.210 ns) 7.729 ns lcd:inst\|reduce_nor~380 7 COMB LCCOMB_X25_Y3_N22 7 " "Info: 7: + IC(0.360 ns) + CELL(0.210 ns) = 7.729 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.570 ns" { lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.989 ns) 9.058 ns lcd:inst\|clkdiv 8 REG LCFF_X25_Y3_N19 2 " "Info: 8: + IC(0.340 ns) + CELL(0.989 ns) = 9.058 ns; Loc. = LCFF_X25_Y3_N19; Fanout = 2; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.329 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.000 ns) 10.075 ns lcd:inst\|clkdiv~clkctrl 9 COMB CLKCTRL_G15 2 " "Info: 9: + IC(1.017 ns) + CELL(0.000 ns) = 10.075 ns; Loc. = CLKCTRL_G15; Fanout = 2; COMB Node = 'lcd:inst\|clkdiv~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.017 ns" { lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.679 ns) 11.845 ns lcd:inst\|clk_int 10 REG LCFF_X25_Y1_N13 2 " "Info: 10: + IC(1.091 ns) + CELL(0.679 ns) = 11.845 ns; Loc. = LCFF_X25_Y1_N13; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.770 ns" { lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.334 ns 45.03 % " "Info: Total cell delay = 5.334 ns ( 45.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.511 ns 54.97 % " "Info: Total interconnect delay = 6.511 ns ( 54.97 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "11.845 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.845 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } { 0.0ns 0.0ns 0.117ns 1.089ns 0.978ns 1.089ns 0.43ns 0.36ns 0.34ns 1.017ns 1.091ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.378ns 0.21ns 0.989ns 0.0ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "12.879 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.879 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } { 0.0ns 0.0ns 0.117ns 1.089ns 0.978ns 1.089ns 0.77ns 0.37ns 0.34ns 1.017ns 1.091ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.636ns 0.636ns 0.989ns 0.0ns 0.679ns } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "11.845 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.845 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } { 0.0ns 0.0ns 0.117ns 1.089ns 0.978ns 1.089ns 0.43ns 0.36ns 0.34ns 1.017ns 1.091ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.378ns 0.21ns 0.989ns 0.0ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns - " "Info: - Micro clock to output delay of source is 0.310 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.511 ns - Shortest register register " "Info: - Shortest register to register delay is 0.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|clk_int 1 REG LCFF_X25_Y1_N13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N13; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.401 ns) 0.401 ns lcd:inst\|clk_int~2 2 COMB LCCOMB_X25_Y1_N12 1 " "Info: 2: + IC(0.000 ns) + CELL(0.401 ns) = 0.401 ns; Loc. = LCCOMB_X25_Y1_N12; Fanout = 1; COMB Node = 'lcd:inst\|clk_int~2'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.401 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 0.511 ns lcd:inst\|clk_int 3 REG LCFF_X25_Y1_N13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.110 ns) = 0.511 ns; Loc. = LCFF_X25_Y1_N13; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.110 ns" { lcd:inst|clk_int~2 lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.511 ns 100.00 % " "Info: Total cell delay = 0.511 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.511 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.511 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 lcd:inst|clk_int } { 0.0ns 0.0ns 0.0ns } { 0.0ns 0.401ns 0.11ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.211 ns + " "Info: + Micro hold delay of destination is 0.211 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "12.879 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.879 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } { 0.0ns 0.0ns 0.117ns 1.089ns 0.978ns 1.089ns 0.77ns 0.37ns 0.34ns 1.017ns 1.091ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.636ns 0.636ns 0.989ns 0.0ns 0.679ns } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "11.845 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.845 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } { 0.0ns 0.0ns 0.117ns 1.089ns 0.978ns 1.089ns 0.43ns 0.36ns 0.34ns 1.017ns 1.091ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.0ns 0.989ns 0.378ns 0.21ns 0.989ns 0.0ns 0.679ns } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.511 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 lcd:inst|clk_int } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.511 ns" { lcd:inst|clk_int lcd:inst|clk_int~2 lcd:inst|clk_int } { 0.0ns 0.0ns 0.0ns } { 0.0ns 0.401ns 0.11ns } } }  } 0}