proj.fit.qmsg

液晶模块输出VHDL程序 程序实现的功能是标准的16×2字符型液晶模块上显示字符串

{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 2 31 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  31 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 43 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 40 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 39 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 35 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  35 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 1 39 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.30V 12 31 " "Info: I/O bank number 8 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  31 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.286 ns register register " "Info: Estimated most critical path is register to register delay of 5.286 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|clkcnt\[0\] 1 REG LAB_X25_Y3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y3; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[0\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|clkcnt[0] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.973 ns) + CELL(0.626 ns) 1.599 ns lcd:inst\|add~850 2 COMB LAB_X24_Y3 2 " "Info: 2: + IC(0.973 ns) + CELL(0.626 ns) = 1.599 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~850'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.599 ns" { lcd:inst|clkcnt[0] lcd:inst|add~850 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.738 ns lcd:inst\|add~852 3 COMB LAB_X24_Y3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.139 ns) = 1.738 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~852'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~850 lcd:inst|add~852 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 1.877 ns lcd:inst\|add~854 4 COMB LAB_X24_Y3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.139 ns) = 1.877 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~854'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~852 lcd:inst|add~854 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.016 ns lcd:inst\|add~856 5 COMB LAB_X24_Y3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.139 ns) = 2.016 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~856'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~854 lcd:inst|add~856 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.155 ns lcd:inst\|add~858 6 COMB LAB_X24_Y3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.139 ns) = 2.155 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~858'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~856 lcd:inst|add~858 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.294 ns lcd:inst\|add~860 7 COMB LAB_X24_Y3 2 " "Info: 7: + IC(0.000 ns) + CELL(0.139 ns) = 2.294 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~860'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~858 lcd:inst|add~860 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.433 ns lcd:inst\|add~862 8 COMB LAB_X24_Y3 2 " "Info: 8: + IC(0.000 ns) + CELL(0.139 ns) = 2.433 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~862'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~860 lcd:inst|add~862 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.572 ns lcd:inst\|add~864 9 COMB LAB_X24_Y3 2 " "Info: 9: + IC(0.000 ns) + CELL(0.139 ns) = 2.572 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~864'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~862 lcd:inst|add~864 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.711 ns lcd:inst\|add~866 10 COMB LAB_X24_Y3 2 " "Info: 10: + IC(0.000 ns) + CELL(0.139 ns) = 2.711 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~866'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~864 lcd:inst|add~866 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.850 ns lcd:inst\|add~868 11 COMB LAB_X24_Y3 2 " "Info: 11: + IC(0.000 ns) + CELL(0.139 ns) = 2.850 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~868'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~866 lcd:inst|add~868 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 2.989 ns lcd:inst\|add~870 12 COMB LAB_X24_Y3 2 " "Info: 12: + IC(0.000 ns) + CELL(0.139 ns) = 2.989 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~870'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~868 lcd:inst|add~870 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 3.128 ns lcd:inst\|add~872 13 COMB LAB_X24_Y3 2 " "Info: 13: + IC(0.000 ns) + CELL(0.139 ns) = 3.128 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~872'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~870 lcd:inst|add~872 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 3.267 ns lcd:inst\|add~874 14 COMB LAB_X24_Y3 2 " "Info: 14: + IC(0.000 ns) + CELL(0.139 ns) = 3.267 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~874'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~872 lcd:inst|add~874 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 3.406 ns lcd:inst\|add~876 15 COMB LAB_X24_Y3 2 " "Info: 15: + IC(0.000 ns) + CELL(0.139 ns) = 3.406 ns; Loc. = LAB_X24_Y3; Fanout = 2; COMB Node = 'lcd:inst\|add~876'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~874 lcd:inst|add~876 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.139 ns) 3.545 ns lcd:inst\|add~878 16 COMB LAB_X24_Y3 1 " "Info: 16: + IC(0.000 ns) + CELL(0.139 ns) = 3.545 ns; Loc. = LAB_X24_Y3; Fanout = 1; COMB Node = 'lcd:inst\|add~878'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.139 ns" { lcd:inst|add~876 lcd:inst|add~878 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.516 ns) 4.061 ns lcd:inst\|add~879 17 COMB LAB_X24_Y3 1 " "Info: 17: + IC(0.000 ns) + CELL(0.516 ns) = 4.061 ns; Loc. = LAB_X24_Y3; Fanout = 1; COMB Node = 'lcd:inst\|add~879'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.516 ns" { lcd:inst|add~878 lcd:inst|add~879 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.664 ns) 5.176 ns lcd:inst\|clkcnt~482 18 COMB LAB_X25_Y3 1 " "Info: 18: + IC(0.451 ns) + CELL(0.664 ns) = 5.176 ns; Loc. = LAB_X25_Y3; Fanout = 1; COMB Node = 'lcd:inst\|clkcnt~482'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.115 ns" { lcd:inst|add~879 lcd:inst|clkcnt~482 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 5.286 ns lcd:inst\|clkcnt\[15\] 19 REG LAB_X25_Y3 2 " "Info: 19: + IC(0.000 ns) + CELL(0.110 ns) = 5.286 ns; Loc. = LAB_X25_Y3; Fanout = 2; REG Node = 'lcd:inst\|clkcnt\[15\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.110 ns" { lcd:inst|clkcnt~482 lcd:inst|clkcnt[15] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.862 ns 73.06 % " "Info: Total cell delay = 3.862 ns ( 73.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.424 ns 26.94 % " "Info: Total interconnect delay = 1.424 ns ( 26.94 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "5.286 ns" { lcd:inst|clkcnt[0] lcd:inst|add~850 lcd:inst|add~852 lcd:inst|add~854 lcd:inst|add~856 lcd:inst|add~858 lcd:inst|add~860 lcd:inst|add~862 lcd:inst|add~864 lcd:inst|add~866 lcd:inst|add~868 lcd:inst|add~870 lcd:inst|add~872 lcd:inst|add~874 lcd:inst|add~876 lcd:inst|add~878 lcd:inst|add~879 lcd:inst|clkcnt~482 lcd:inst|clkcnt[15] } "NODE_NAME" } "" } }  } 0}