proj.fit.qmsg

液晶模块输出VHDL程序 程序实现的功能是标准的16×2字符型液晶模块上显示字符串

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 05 14:53:33 2006 " "Info: Processing started: Tue Dec 05 14:53:33 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off LCD_Test -c Proj " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LCD_Test -c Proj" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Proj EP2C20F484C8 " "Info: Selected device EP2C20F484C8 for design \"Proj\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C20F484I8 " "Info: Device EP2C20F484I8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C8 " "Info: Device EP2C35F484C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484I8 " "Info: Device EP2C35F484I8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C8 " "Info: Device EP2C50F484C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484I8 " "Info: Device EP2C50F484I8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 14 " "Info: No exact pin location assignment(s) for 1 pins of 14 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "LCD_DIR " "Info: Pin LCD_DIR not assigned to an exact location on the device" {  } { { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 352 784 960 368 "LCD_DIR" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "LCD_DIR" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { LCD_DIR } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { LCD_DIR } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN W12 (CLK13, LVDSCLK6p, Input)) " "Info: Automatically promoted node clk (placed in PIN W12 (CLK13, LVDSCLK6p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G14 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14" {  } {  } 0}  } { { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { clk } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "lcd:inst\|clk_int  " "Info: Automatically promoted node lcd:inst\|clk_int " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd:inst\|clk_int~2 " "Info: Destination node lcd:inst\|clk_int~2" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int~2" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|clk_int~2 } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { lcd:inst|clk_int~2 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|clk_int } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { lcd:inst|clk_int } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "div16:inst2\|count\[3\]  " "Info: Automatically promoted node div16:inst2\|count\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "div16:inst2\|count\[3\]~8 " "Info: Destination node div16:inst2\|count\[3\]~8" {  } { { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst2\|count\[3\]~8" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { div16:inst2|count[3]~8 } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { div16:inst2|count[3]~8 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst2\|count\[3\]" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { div16:inst2|count[3] } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { div16:inst2|count[3] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "lcd:inst\|clkdiv  " "Info: Automatically promoted node lcd:inst\|clkdiv " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lcd:inst\|clkdiv~2 " "Info: Destination node lcd:inst\|clkdiv~2" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv~2" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|clkdiv~2 } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { lcd:inst|clkdiv~2 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv" } } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|clkdiv } "NODE_NAME" } "" } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.fld" "" "" { lcd:inst|clkdiv } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}