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📄 signal.lst

📁 简易信号发生器+Protues仿真,函数波形发生器产生波形表
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     140 9199      LD	R25,Y+
     141 9189      LD	R24,Y+
     142 9059      LD	R5,Y+
     143 9049      LD	R4,Y+
     144 9039      LD	R3,Y+
     145 9029      LD	R2,Y+
     146 9518      RETI
(0105) } 
(0106) 
(0107) 
(0108) //call this routine to initialize all peripherals
(0109) void init_devices(void)
(0110) {
(0111)  //stop errant interrupts until set up
(0112)  CLI(); //disable all interrupts
_init_devices:
     147 94F8      BCLR	7
(0113)  port_init();
     148 DF82      RCALL	_port_init
(0114)  timer1_init();
     149 DF8D      RCALL	_timer1_init
(0115) 
(0116)  MCUCR = 0x02;
     14A E082      LDI	R24,2
     14B BF85      OUT	0x35,R24
(0117)  EMCUCR = 0x00;
     14C 2422      CLR	R2
     14D BE26      OUT	0x36,R2
(0118)  GICR = 0x40;
     14E E480      LDI	R24,0x40
     14F BF8B      OUT	0x3B,R24
(0119)  TIMSK = 0x80;
     150 E880      LDI	R24,0x80
     151 BF89      OUT	0x39,R24
(0120)  SEI(); //re-enable interrupts
     152 9478      BSET	7
     153 9508      RET
(0121)  //all peripherals are now initialized
(0122) }
(0123) 
(0124) void key_read()
(0125) {
(0126)   uchar num,i;
(0127)   DDRA=0xff;     // 都定义为输出
_key_read:
  num                  --> Y,+1
  i                    --> R16
     154 EF8F      LDI	R24,0xFF
     155 BB8A      OUT	0x1A,R24
(0128)   PORTA=0xf0;   // 高位输出高电平,低位输出低电平
     156 EF80      LDI	R24,0xF0
     157 BB8B      OUT	0x1B,R24
(0129)   DDRA=0x0f;  // 有键按下,把相应列(高位)的电平拉低
     158 E08F      LDI	R24,0xF
     159 BB8A      OUT	0x1A,R24
(0130)   asm("nop");
     15A 0000      NOP
(0131)   i=PINA;    //获取列的地址,即
     15B B309      IN	R16,0x19
(0132)   DDRA=0xff;
     15C EF8F      LDI	R24,0xFF
     15D BB8A      OUT	0x1A,R24
(0133)   PORTA=0x0f;
     15E E08F      LDI	R24,0xF
     15F BB8B      OUT	0x1B,R24
(0134)   DDRA=0xf0;  //把相应行的电平拉低
     160 EF80      LDI	R24,0xF0
     161 BB8A      OUT	0x1A,R24
(0135)   asm("nop");
     162 0000      NOP
(0136)   i|=PINA;     //获取行的地址 ,行与列的地址决定按键的位置
     163 B229      IN	R2,0x19
     164 2902      OR	R16,R2
(0137)   switch(i)
     165 2711      CLR	R17
     166 3B0B      CPI	R16,0xBB
     167 E0E0      LDI	R30,0
     168 071E      CPC	R17,R30
     169 F409      BNE	0x016B
     16A C068      RJMP	0x01D3
     16B 3B0D      CPI	R16,0xBD
     16C E0E0      LDI	R30,0
     16D 071E      CPC	R17,R30
     16E F409      BNE	0x0170
     16F C063      RJMP	0x01D3
     170 EB8D      LDI	R24,0xBD
     171 E090      LDI	R25,0
     172 1780      CP	R24,R16
     173 0791      CPC	R25,R17
     174 F0D4      BLT	0x018F
     175 370B      CPI	R16,0x7B
     176 E0E0      LDI	R30,0
     177 071E      CPC	R17,R30
     178 F409      BNE	0x017A
     179 C03C      RJMP	0x01B6
     17A 370D      CPI	R16,0x7D
     17B E0E0      LDI	R30,0
     17C 071E      CPC	R17,R30
     17D F409      BNE	0x017F
     17E C046      RJMP	0x01C5
     17F E78D      LDI	R24,0x7D
     180 E090      LDI	R25,0
     181 1780      CP	R24,R16
     182 0791      CPC	R25,R17
     183 F02C      BLT	0x0189
     184 3707      CPI	R16,0x77
     185 E0E0      LDI	R30,0
     186 071E      CPC	R17,R30
     187 F119      BEQ	0x01AB
     188 C04A      RJMP	0x01D3
     189 3B07      CPI	R16,0xB7
     18A E0E0      LDI	R30,0
     18B 071E      CPC	R17,R30
     18C F409      BNE	0x018E
     18D C045      RJMP	0x01D3
     18E C044      RJMP	0x01D3
     18F 3D0B      CPI	R16,0xDB
     190 E0E0      LDI	R30,0
     191 071E      CPC	R17,R30
     192 F409      BNE	0x0194
     193 C03F      RJMP	0x01D3
     194 ED8B      LDI	R24,0xDB
     195 E090      LDI	R25,0
     196 1780      CP	R24,R16
     197 0791      CPC	R25,R17
     198 F02C      BLT	0x019E
     199 3D07      CPI	R16,0xD7
     19A E0E0      LDI	R30,0
     19B 071E      CPC	R17,R30
     19C F1B1      BEQ	0x01D3
     19D C035      RJMP	0x01D3
     19E 3E07      CPI	R16,0xE7
     19F E0E0      LDI	R30,0
     1A0 071E      CPC	R17,R30
     1A1 F189      BEQ	0x01D3
     1A2 3E07      CPI	R16,0xE7
     1A3 E0E0      LDI	R30,0
     1A4 071E      CPC	R17,R30
     1A5 F16C      BLT	0x01D3
     1A6 3E0B      CPI	R16,0xEB
     1A7 E0E0      LDI	R30,0
     1A8 071E      CPC	R17,R30
     1A9 F149      BEQ	0x01D3
     1AA C028      RJMP	0x01D3
(0138)   {
(0139) 	case 0x77 : 
(0140) 	{
(0141) 	  func++; 
     1AB 9180 0069 LDS	R24,func
     1AD 5F8F      SUBI	R24,0xFF
     1AE 9380 0069 STS	func,R24
(0142) 	  if(func==4) 
     1B0 3084      CPI	R24,4
     1B1 F509      BNE	0x01D3
(0143) 	  func=0x00;  break;
     1B2 2422      CLR	R2
     1B3 9220 0069 STS	func,R2
     1B5 C01D      RJMP	0x01D3
(0144) 	}	
(0145) 	case 0x7B :       //频率加250Hz
(0146)     {
(0147)       th1-=f1;
     1B6 9020 0065 LDS	R2,f1
     1B8 9030 0063 LDS	R3,th1
     1BA 1832      SUB	R3,R2
     1BB 9230 0063 STS	th1,R3
(0148) 	  tl1-=f2;
     1BD 9020 0066 LDS	R2,f2
     1BF 9030 0064 LDS	R3,tl1
     1C1 1832      SUB	R3,R2
     1C2 9230 0064 STS	tl1,R3
(0149) 	  break;
     1C4 C00E      RJMP	0x01D3
(0150)     } 
(0151) 	case 0x7D :      ////频率减250Hz
(0152) 	 {
(0153) 	   th1+=f1;
     1C5 9020 0065 LDS	R2,f1
     1C7 9030 0063 LDS	R3,th1
     1C9 0C32      ADD	R3,R2
     1CA 9230 0063 STS	th1,R3
(0154) 	   tl1+=f2;
     1CC 9020 0066 LDS	R2,f2
     1CE 9030 0064 LDS	R3,tl1
     1D0 0C32      ADD	R3,R2
     1D1 9230 0064 STS	tl1,R3
(0155) 	   break;
(0156) 	 }
(0157) 	/*case 0xEE : 
(0158) 	{
(0159) 	  func++; 
(0160) 	  if(func==4) 
(0161) 	  func=0x00;  break;
(0162) 	}
(0163) 	case 0xDE : 
(0164) 	{
(0165) 	  func++; 
(0166) 	  if(func==4) 
(0167) 	  func=0x00; break;
(0168) 	}
(0169) 	case 0xBE : 
(0170)     {
(0171) 	  func++; 
(0172) 	  if(func==4) 
(0173) 	  func=0x00; break;
(0174) 	}
(0175) 	case 0x7E : 
(0176)     {
(0177) 	  func++; 
(0178) 	  if(func==4) 
(0179) 	  func=0x00; break;
(0180) 	}
(0181) 	case 0xED : 
(0182) 	{
(0183) 	  func++; 
(0184) 	  if(func==4) 
(0185) 	  func=0x00; break;
(0186) 	}	
(0187) 	case 0xDD : 
(0188) 	{
(0189) 	  func++; 
(0190) 	  if(func==4) 
(0191) 	  func=0x00; break;
(0192) 	}	*/
(0193) 	case 0xBD : ; break;
(0194) 	case 0xEB : ; break;
(0195) 	case 0xDB : ; break;
(0196) 	case 0xBB : ; break;
(0197) 	case 0xE7 : ; break;
(0198) 	case 0xD7 : ; break;
(0199) 	case 0xB7 : ; break;
(0200) 
(0201) 	
(0202) 	default : break;
     1D3 9508      RET
(0203)    }
(0204) 
(0205) }
(0206) 
(0207) 
(0208) void main()
(0209) {
(0210)    //set_cw1;
(0211)    //set_xwr2;
(0212)    init_devices();
_main:
     1D4 DF72      RCALL	_init_devices
     1D5 C001      RJMP	0x01D7
(0213)    while(1)
(0214)     { 
(0215) 	  key_read();
FILE: <library>
     1D6 DF7D      RCALL	_key_read
     1D7 CFFE      RJMP	0x01D6
     1D8 9508      RET
push_xgsetF000:
     1D9 937A      ST	R23,-Y
     1DA 936A      ST	R22,-Y
     1DB 935A      ST	R21,-Y
     1DC 934A      ST	R20,-Y
     1DD 9508      RET
pop_xgsetF000:
     1DE 9149      LD	R20,Y+
     1DF 9159      LD	R21,Y+
     1E0 9169      LD	R22,Y+
     1E1 9179      LD	R23,Y+
     1E2 9508      RET

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