📄 reset.cpp
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/*******************************************************************************
*
* ViP model for FIMGSE
* version 1.0
*
* Reset.c
*
* by inhosens.lee
* Graphics IP Team in XG, Mobile Solution Development,
* System LSI Division, Semiconductor Business,
* Samsung Electronics
*
* Copyright (c) 2005 FIMG team
*
* All rights reserved. No part of this program may be reproduced, stored
* in a retrieval system, or tranmitted, in any form or by any means,
* electronic, mechanical, photocopying, recording, or otherwise, without
* the prior written permission of the author.
*
* 2006. 1. 28 by cheolkyoo.kim
*
* Description
*
* $RCSfile: Reset.cpp,v $
* $Revision: 1.1 $
* $Author: inhosens.lee $
* $Date: 2006/06/02 00:39:36 $
* $Locker: $
*
* $Source: C:/CVS/CVSrepository/FIMG-3DSE_SW/fimg3dse_fpga/fimg3d/src/Reset.cpp,v $
* $State: Exp $
* $Log: Reset.cpp,v $
* Revision 1.1 2006/06/02 00:39:36 inhosens.lee
* SWReset Function
*
*
******************************************************************************/
/****************************************************************************
* INCLUDES
****************************************************************************/
//-daedoo
//#include "g3d.h"
#include "fimg_defs.h"
/****************************************************************************
* DEFINES
****************************************************************************/
#if 0
static default_reg psDefaultGBRegs[] =
{
{ FIMG_GBREG_SWRESET, {FIMG_GLOBREG_SWRESET, 0xFFFFFFFF} },
{ FIMG_GBREG_PIPESTATE, {FIMG_GLOBREG_PIPESTATE, 0} },
{ FIMG_GBREG_CACHE_ENABLE, {FIMG_GLOBREG_CACHEENABLE, 0} },
{ FIMG_GBREG_INT_ENABLE, {FIMG_GLOBREG_INTENABLE, 0} },
{ FIMG_GBREG_INT_COND, {FIMG_GLOBREG_INTCOND, 0} }
};
#endif
static default_reg hi_default_regs[] =
{
{ r_hi_ctrl, {FGHI_HI_CTRL, 0} },
{ r_idx_offset, {FGHI_IDX_OFFSET, 0} },
{ r_attr0, {FGHI_ATTR0, 0} },
{ r_attr1, {FGHI_ATTR1, 0} },
{ r_attr2, {FGHI_ATTR2, 0} },
{ r_attr3, {FGHI_ATTR3, 0} },
{ r_attr4, {FGHI_ATTR4, 0} },
{ r_attr5, {FGHI_ATTR5, 0} },
{ r_attr6, {FGHI_ATTR6, 0} },
{ r_attr7, {FGHI_ATTR7, 0} },
{ r_attr8, {FGHI_ATTR8, 0} },
{ r_attr9, {FGHI_ATTR9, 0} },
{ r_attra, {FGHI_ATTRA, 0} },
{ r_attrb, {FGHI_ATTRB, 0} },
{ r_attrc, {FGHI_ATTRC, 0} },
{ r_attrd, {FGHI_ATTRD, 0} },
{ r_attre, {FGHI_ATTRE, 0} },
{ r_attrf, {FGHI_ATTRF, 0} },
{ r_vtxbuf_ctrl0, {FGHI_VTXBUF_CTRL0, 0} },
{ r_vtxbuf_ctrl1, {FGHI_VTXBUF_CTRL1, 0} },
{ r_vtxbuf_ctrl2, {FGHI_VTXBUF_CTRL2, 0} },
{ r_vtxbuf_ctrl3, {FGHI_VTXBUF_CTRL3, 0} },
{ r_vtxbuf_ctrl4, {FGHI_VTXBUF_CTRL4, 0} },
{ r_vtxbuf_ctrl5, {FGHI_VTXBUF_CTRL5, 0} },
{ r_vtxbuf_ctrl6, {FGHI_VTXBUF_CTRL6, 0} },
{ r_vtxbuf_ctrl7, {FGHI_VTXBUF_CTRL7, 0} },
{ r_vtxbuf_ctrl8, {FGHI_VTXBUF_CTRL8, 0} },
{ r_vtxbuf_ctrl9, {FGHI_VTXBUF_CTRL9, 0} },
{ r_vtxbuf_ctrla, {FGHI_VTXBUF_CTRLA, 0} },
{ r_vtxbuf_ctrlb, {FGHI_VTXBUF_CTRLB, 0} },
{ r_vtxbuf_ctrlc, {FGHI_VTXBUF_CTRLC, 0} },
{ r_vtxbuf_ctrld, {FGHI_VTXBUF_CTRLD, 0} },
{ r_vtxbuf_ctrle, {FGHI_VTXBUF_CTRLE, 0} },
{ r_vtxbuf_ctrlf, {FGHI_VTXBUF_CTRLF, 0} },
{ r_vtxbuf_base0, {FGHI_VTXBUF_BASE0, 0} },
{ r_vtxbuf_base1, {FGHI_VTXBUF_BASE1, 0} },
{ r_vtxbuf_base2, {FGHI_VTXBUF_BASE2, 0} },
{ r_vtxbuf_base3, {FGHI_VTXBUF_BASE3, 0} },
{ r_vtxbuf_base4, {FGHI_VTXBUF_BASE4, 0} },
{ r_vtxbuf_base5, {FGHI_VTXBUF_BASE5, 0} },
{ r_vtxbuf_base6, {FGHI_VTXBUF_BASE6, 0} },
{ r_vtxbuf_base7, {FGHI_VTXBUF_BASE7, 0} },
{ r_vtxbuf_base8, {FGHI_VTXBUF_BASE8, 0} },
{ r_vtxbuf_base9, {FGHI_VTXBUF_BASE9, 0} },
{ r_vtxbuf_basea, {FGHI_VTXBUF_BASEA, 0} },
{ r_vtxbuf_baseb, {FGHI_VTXBUF_BASEB, 0} },
{ r_vtxbuf_basec, {FGHI_VTXBUF_BASEC, 0} },
{ r_vtxbuf_based, {FGHI_VTXBUF_BASED, 0} },
{ r_vtxbuf_basee, {FGHI_VTXBUF_BASEE, 0} },
{ r_vtxbuf_basef, {FGHI_VTXBUF_BASEF, 0} }
};
static default_reg vs_default_regs[] =
{
{r_config, {FGVS_CONFIG, 0}},
{r_status, {FGVS_STATUS, 0}},
{r_pc_range, {FGVS_PC_RANGE, 0}},
{r_vs_attrib_num, {FGVS_ATTRIB_NUM, 0}},
{r_in_attrib_idx0, {FGVS_IN_ATTRIB_IDX0, 0}},
{r_in_attrib_idx1, {FGVS_IN_ATTRIB_IDX1, 0}},
{r_in_attrib_idx2, {FGVS_IN_ATTRIB_IDX2, 0}},
{r_out_attrib_idx0, {FGVS_OUT_ATTRIB_IDX0, 0}},
{r_out_attrib_idx1, {FGVS_OUT_ATTRIB_IDX1, 0}},
{r_out_attrib_idx2, {FGVS_OUT_ATTRIB_IDX2, 0}}
};
static shader_slot vs_shader_slots[] =
{
{r_shader_instruction_slot, {FGVS_INSTMEM_SADDR, FGVS_INSTMEM_EADDR, FGVS_INSTMEM_SIZE}},
{r_shader_const_float_slot, {FGVS_CFLOAT_SADDR, FGVS_CFLOAT_EADDR, FGVS_CFLOAT_SIZE}},
{r_shader_const_int_slot, {FGVS_CINT_SADDR, FGVS_CINT_EADDR, FGVS_CINT_SIZE}},
{r_shader_const_bool_slot, {FGVS_CBOOL_SADDR, FGVS_CBOOL_EADDR, FGVS_CBOOL_SIZE}}
};
static default_reg pe_default_regs[] =
{
{r_vtx_context, {FGPE_VTX_CONTEXT, 0}},
{r_viewport_center_xcord, {FGPE_VIEWPORT_CENTER_XCOORD, 0}},
{r_viewport_center_ycord, {FGPE_VIEWPORT_CENTER_YCOORD, 0}},
{r_viewport_half_width, {FGPE_VIEWPORT_HALF_WIDTH, 0}},
{r_viewport_half_height, {FGPE_VIEWPORT_HALF_HEIGHT, 0}},
{r_depth_half_distance, {FGPE_DEPTH_HALF_DISTANCE, 0x3F000000}},
{r_depth_center, {FGPE_DEPTH_CENTER, 0x3F000000}}
};
static default_reg ra_default_regs[] =
{
{r_pixel_sampos, {FGRA_PIXEL_SAMPOS, 0}},
{r_depth_offset_en, {FGRA_DEPTH_OFFSET_EN, 0}},
{r_depth_offset_factor, {FGRA_DEPTH_OFFSET_FACTOR, 0}},
{r_depth_offset_unit, {FGRA_DEPTH_OFFSET_UNIT, 0}},
{r_depth_offset_rval, {FGRA_DEPTH_OFFSET_RVAL, 0x33800002}},
{r_backface_cull, {FGRA_BACKFACE_CULL, 0}},
{r_clip_ycord, {FGRA_CLIP_YCORD, 0}},
{r_lod_ctrl, {FGRA_LOD_CTRL, 0}},
{r_clip_xcord, {FGRA_CLIP_XCORD, 0}}
#ifdef _FIMG_V_1_1
,
{r_point_width, {FGRA_POINT_WIDTH, 0x3F800000}},
{r_point_size_min, {FGRA_POINT_SIZE_MIN, 0x3F800000}},
{r_point_size_max, {FGRA_POINT_SIZE_MAX, 0x45000000}},
{r_coord_replace, {FGRA_COORD_REPLACE, 0x0}},
{r_line_width, {FGRA_LINE_WIDTH, 0x3F800000}}
#endif
};
static default_reg ps_default_regs[] =
{
{r_exe_mode, {FGPS_EXE_MODE, 0}},
{r_pc_start, {FGPS_PC_START, 0}},
{r_pc_end, {FGPS_PC_END, 0}},
{r_pc_copy, {FGPS_PC_COPY, 0}},
{r_ps_attrib_num, {FGPS_ATTRIB_NUM, 0}},
{r_inbuf_status, {FGPS_INBUF_STATUS, 0}}
};
static shader_slot ps_shader_slots[] =
{
{r_shader_instruction_slot, {FGPS_INSTMEM_SADDR, FGPS_INSTMEM_EADDR, FGPS_INSTMEM_SIZE}},
{r_shader_const_float_slot, {FGPS_CFLOAT_SADDR, FGPS_CFLOAT_EADDR, FGPS_CFLOAT_SIZE}},
{r_shader_const_int_slot, {FGPS_CINT_SADDR, FGPS_CINT_EADDR, FGPS_CINT_SIZE}},
{r_shader_const_bool_slot, {FGPS_CBOOL_SADDR, FGPS_CBOOL_EADDR, FGPS_CBOOL_SIZE}}
};
static default_reg tu_default_regs[] =
{
{r_tex0_ctrl, {FGTU_TEX0_CTRL, 0}},
{r_tex0_base_level, {FGTU_TEX0_BASE_LEVEL, 0}},
{r_tex0_max_level, {FGTU_TEX0_MAX_LEVEL, 0}},
{r_tex0_base_addr, {FGTU_TEX0_BASE_ADDR, 0}},
{r_tex1_ctrl, {FGTU_TEX1_CTRL, 0}},
{r_tex1_base_level, {FGTU_TEX1_BASE_LEVEL, 0}},
{r_tex1_max_level, {FGTU_TEX1_MAX_LEVEL, 0}},
{r_tex1_base_addr, {FGTU_TEX1_BASE_ADDR, 0}},
{r_tex2_ctrl, {FGTU_TEX2_CTRL, 0}},
{r_tex2_base_level, {FGTU_TEX2_BASE_LEVEL, 0}},
{r_tex2_max_level, {FGTU_TEX2_MAX_LEVEL, 0}},
{r_tex2_base_addr, {FGTU_TEX2_BASE_ADDR, 0}},
{r_tex3_ctrl, {FGTU_TEX3_CTRL, 0}},
{r_tex3_base_level, {FGTU_TEX3_BASE_LEVEL, 0}},
{r_tex3_max_level, {FGTU_TEX3_MAX_LEVEL, 0}},
{r_tex3_base_addr, {FGTU_TEX3_BASE_ADDR, 0}},
{r_tex4_ctrl, {FGTU_TEX4_CTRL, 0}},
{r_tex4_base_level, {FGTU_TEX4_BASE_LEVEL, 0}},
{r_tex4_max_level, {FGTU_TEX4_MAX_LEVEL, 0}},
{r_tex4_base_addr, {FGTU_TEX4_BASE_ADDR, 0}},
{r_tex5_ctrl, {FGTU_TEX5_CTRL, 0}},
{r_tex5_base_level, {FGTU_TEX5_BASE_LEVEL, 0}},
{r_tex5_max_level, {FGTU_TEX5_MAX_LEVEL, 0}},
{r_tex5_base_addr, {FGTU_TEX5_BASE_ADDR, 0}},
{r_tex6_ctrl, {FGTU_TEX6_CTRL, 0}},
{r_tex6_base_level, {FGTU_TEX6_BASE_LEVEL, 0}},
{r_tex6_max_level, {FGTU_TEX6_MAX_LEVEL, 0}},
{r_tex6_base_addr, {FGTU_TEX6_BASE_ADDR, 0}},
{r_tex7_ctrl, {FGTU_TEX7_CTRL, 0}},
{r_tex7_base_level, {FGTU_TEX7_BASE_LEVEL, 0}},
{r_tex7_max_level, {FGTU_TEX7_MAX_LEVEL, 0}},
{r_tex7_base_addr, {FGTU_TEX7_BASE_ADDR, 0}},
{r_color_key1, {FGTU_COLOR_KEY1, 0}},
{r_color_key2, {FGTU_COLOR_KEY2, 0}},
{r_color_key_yuv, {FGTU_COLOR_KEY_YUV, 0}},
{r_color_key_mask, {FGTU_COLOR_KEY_MASK, 0}},
{r_pallete_addr, {FGTU_PALETTE_ADDR, 0}},
{r_pallete_entry, {FGTU_PALETTE_ENTRY, 0}},
{r_vtxtex0_ctrl, {FGTU_VTXTEX0_CTRL, 0}},
{r_vtxtex0_base_addr, {FGTU_VTXTEX0_BASE_ADDR,0}},
{r_vtxtex1_ctrl, {FGTU_VTXTEX1_CTRL, 0}},
{r_vtxtex1_base_addr, {FGTU_VTXTEX1_BASE_ADDR,0}},
{r_vtxtex2_ctrl, {FGTU_VTXTEX2_CTRL, 0}},
{r_vtxtex2_base_addr, {FGTU_VTXTEX2_BASE_ADDR,0}},
{r_vtxtex3_ctrl, {FGTU_VTXTEX3_CTRL, 0}},
{r_vtxtex3_base_addr, {FGTU_VTXTEX3_BASE_ADDR,0}}
};
static default_reg pf_default_regs[] =
{
{r_scissor_xcord, {FGPF_SCISSOR_XCORD, 0}},
{r_scissor_ycord, {FGPF_SCISSOR_YCORD, 0}},
{r_alpha, {FGPF_ALPHA, 0}},
{r_frontface_stencil, {FGPF_FRONTFACE_STENCIL,0}},
{r_backface_stencil, {FGPF_BACKFACE_STENCIL, 0}},
{r_depth, {FGPF_DEPTH, 0}},
{r_blend_color, {FGPF_BLEND_COLOR, 0}},
{r_blend, {FGPF_BLEND, 0}},
{r_logic_op, {FGPF_LOGIC_OP, 0}},
{r_color_mask, {FGPF_COLOR_MASK, 0}},
{r_depth_mask, {FGPF_DEPTH_MASK, 0}},
{r_colorbuf_ctrl, {FGPF_COLORBUF_CTRL, 0}},
{r_depthbuf_addr, {FGPF_DEPTHBUF_ADDR, 0}},
{r_colorbuf_addr, {FGPF_COLORBUF_ADDR, 0}},
{r_colorbuf_width, {FGPF_COLORBUF_WIDTH, 0}}
};
unsigned int sfr_write(pdefault_reg p_default_reg, unsigned int size);
bool G3D::Reset(void)
{
WRITEREG(FIMG_BASE + 0x00000008, 0x00000001);
sfr_write((pdefault_reg)hi_default_regs, (unsigned int)hi_reg_count);
sfr_write((pdefault_reg)vs_default_regs, (unsigned int)vs_reg_count);
sfr_write((pdefault_reg)pe_default_regs, (unsigned int)pe_reg_count);
sfr_write((pdefault_reg)ra_default_regs, (unsigned int)ra_reg_count);
sfr_write((pdefault_reg)ps_default_regs, (unsigned int)ps_reg_count);
sfr_write((pdefault_reg)tu_default_regs, (unsigned int)tu_reg_count);
sfr_write((pdefault_reg)pf_default_regs, (unsigned int)pf_reg_count);
WRITEREG(FIMG_BASE + 0x00000008, 0x00000000);
return NO_ERROR;
}
unsigned int sfr_write(pdefault_reg p_default_reg, unsigned int size)
{
do
{
WRITEREG(p_default_reg->reg.addr, p_default_reg->reg.val);
++p_default_reg;
} while(--size != 0);
return NO_ERROR;
}
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