pci_top.map.rpt

PIC 的ip 有用的着的拿去看看吧 对于开发pci总线会有很大帮助的

; pcicore:pci_core1|BaseAddress1[23]         ; 2       ;
; pcicore:pci_core1|PciCycleBeginClear_      ; 1       ;
; pcicore:pci_core1|BaseAddress0[26]         ; 2       ;
; pcicore:pci_core1|BaseAddress1[26]         ; 2       ;
; pcicore:pci_core1|BaseAddress0[5]          ; 2       ;
; pcicore:pci_core1|BaseAddress0[6]          ; 2       ;
; pcicore:pci_core1|InterruptLine[6]         ; 1       ;
; Total number of inverted registers = 61    ;         ;
+--------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: pcicore:pci_core1|lpm_counter:INT_SCAN_COUNTER_rtl_0 ;
+------------------------+-------------------+----------------------------------------------------------+
; Parameter Name         ; Value             ; Type                                                     ;
+------------------------+-------------------+----------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                                             ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                                           ;
; LPM_WIDTH              ; 19                ; Untyped                                                  ;
; LPM_DIRECTION          ; UP                ; Untyped                                                  ;
; LPM_MODULUS            ; 0                 ; Untyped                                                  ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                                  ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                                  ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                                  ;
; DEVICE_FAMILY          ; FLEX10KA          ; Untyped                                                  ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                                  ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                                       ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                                       ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                                  ;
; LABWIDE_SCLR           ; ON                ; Untyped                                                  ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                                  ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                                  ;
+------------------------+-------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 10 11:41:47 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pci_top -c pci_top
Warning (10236): Verilog HDL net warning at pci_top.v(135): created undeclared net "PciParOutEnable"
Warning (10236): Verilog HDL net warning at pci_top.v(143): created undeclared net "E8051P0OutEnable"
Warning: Using design file pci_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: pci_top
Info: Elaborating entity "pci_top" for the top level hierarchy
Warning (10030): Tied undriven net "IoWR_" at pci_top.v(93) to 0
Warning: Using design file pcicore.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: pcicore
Info: Elaborating entity "pcicore" for hierarchy "pcicore:pci_core1"
Warning (10235): Verilog HDL Always Construct warning at pcicore.v(569): variable "BUTTON_INT_" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at pcicore.v(586): variable "PciAdressReg" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at pcicore.v(588): variable "Com" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at pcicore.v(590): variable "BaseAddress0" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at pcicore.v(591): variable "BaseAddress1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at pcicore.v(592): variable "InterruptLine" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at pcicore.v(668): truncated value with size 32 to match size of target (19)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=19) from the following logic: "pcicore:pci_core1|INT_SCAN_COUNTER[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "pcicore:pci_core1|lpm_counter:INT_SCAN_COUNTER_rtl_0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "pcicore:pci_core1|lpm_counter:INT_SCAN_COUNTER_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "pcicore:pci_core1|lpm_counter:INT_SCAN_COUNTER_rtl_0"
Info: Instantiated megafunction "pcicore:pci_core1|lpm_counter:INT_SCAN_COUNTER_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "19"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: State machine "|pci_top|pcicore:pci_core1|PciStateMachine" contains 16 states
Info: State machine "|pci_top|pcicore:pci_core1|PciAdOutSelect" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|pci_top|pcicore:pci_core1|PciStateMachine"
Info: Encoding result for state machine "|pci_top|pcicore:pci_core1|PciStateMachine"
    Info: Completed encoding using 16 state bits
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1010"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0001"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1000"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0011"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0111"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1111"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1011"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1100"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0100"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0101"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1001"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1110"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0110"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.1101"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0010"
        Info: Encoded state bit "pcicore:pci_core1|PciStateMachine.0000"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0000" uses code string "0000000000000000"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0010" uses code string "0000000000000011"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1101" uses code string "0000000000000101"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0110" uses code string "0000000000001001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1110" uses code string "0000000000010001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1001" uses code string "0000000000100001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0101" uses code string "0000000001000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0100" uses code string "0000000010000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1100" uses code string "0000000100000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1011" uses code string "0000001000000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1111" uses code string "0000010000000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0111" uses code string "0000100000000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0011" uses code string "0001000000000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1000" uses code string "0010000000000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.0001" uses code string "0100000000000001"
    Info: State "|pci_top|pcicore:pci_core1|PciStateMachine.1010" uses code string "1000000000000001"
Info: Selected Auto state machine encoding method for state machine "|pci_top|pcicore:pci_core1|PciAdOutSelect"
Info: Encoding result for state machine "|pci_top|pcicore:pci_core1|PciAdOutSelect"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "pcicore:pci_core1|PciAdOutSelect.00"
        Info: Encoded state bit "pcicore:pci_core1|PciAdOutSelect.10"
        Info: Encoded state bit "pcicore:pci_core1|PciAdOutSelect.01"
    Info: State "|pci_top|pcicore:pci_core1|PciAdOutSelect.00" uses code string "000"
    Info: State "|pci_top|pcicore:pci_core1|PciAdOutSelect.01" uses code string "101"
    Info: State "|pci_top|pcicore:pci_core1|PciAdOutSelect.10" uses code string "110"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "IoWR_" stuck at GND
    Warning: Pin "CS_LED" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 449 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 29 output pins
    Info: Implemented 40 bidirectional pins
    Info: Implemented 370 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Processing ended: Tue Apr 10 11:41:51 2007
    Info: Elapsed time: 00:00:04