pci_top.hier_info

PIC 的ip 有用的着的拿去看看吧 对于开发pci总线会有很大帮助的

|pci_top
CLK => CLK~0.IN1
RESET_ => RESET_~0.IN1
AD[0] <= pcicore:pci_core1.PciAdIn
AD[0] <= AD~63
AD[1] <= pcicore:pci_core1.PciAdIn
AD[1] <= AD~62
AD[2] <= pcicore:pci_core1.PciAdIn
AD[2] <= AD~61
AD[3] <= pcicore:pci_core1.PciAdIn
AD[3] <= AD~60
AD[4] <= pcicore:pci_core1.PciAdIn
AD[4] <= AD~59
AD[5] <= pcicore:pci_core1.PciAdIn
AD[5] <= AD~58
AD[6] <= pcicore:pci_core1.PciAdIn
AD[6] <= AD~57
AD[7] <= pcicore:pci_core1.PciAdIn
AD[7] <= AD~56
AD[8] <= pcicore:pci_core1.PciAdIn
AD[8] <= AD~55
AD[9] <= pcicore:pci_core1.PciAdIn
AD[9] <= AD~54
AD[10] <= pcicore:pci_core1.PciAdIn
AD[10] <= AD~53
AD[11] <= pcicore:pci_core1.PciAdIn
AD[11] <= AD~52
AD[12] <= pcicore:pci_core1.PciAdIn
AD[12] <= AD~51
AD[13] <= pcicore:pci_core1.PciAdIn
AD[13] <= AD~50
AD[14] <= pcicore:pci_core1.PciAdIn
AD[14] <= AD~49
AD[15] <= pcicore:pci_core1.PciAdIn
AD[15] <= AD~48
AD[16] <= pcicore:pci_core1.PciAdIn
AD[16] <= AD~47
AD[17] <= pcicore:pci_core1.PciAdIn
AD[17] <= AD~46
AD[18] <= pcicore:pci_core1.PciAdIn
AD[18] <= AD~45
AD[19] <= pcicore:pci_core1.PciAdIn
AD[19] <= AD~44
AD[20] <= pcicore:pci_core1.PciAdIn
AD[20] <= AD~43
AD[21] <= pcicore:pci_core1.PciAdIn
AD[21] <= AD~42
AD[22] <= pcicore:pci_core1.PciAdIn
AD[22] <= AD~41
AD[23] <= pcicore:pci_core1.PciAdIn
AD[23] <= AD~40
AD[24] <= pcicore:pci_core1.PciAdIn
AD[24] <= AD~39
AD[25] <= pcicore:pci_core1.PciAdIn
AD[25] <= AD~38
AD[26] <= pcicore:pci_core1.PciAdIn
AD[26] <= AD~37
AD[27] <= pcicore:pci_core1.PciAdIn
AD[27] <= AD~36
AD[28] <= pcicore:pci_core1.PciAdIn
AD[28] <= AD~35
AD[29] <= pcicore:pci_core1.PciAdIn
AD[29] <= AD~34
AD[30] <= pcicore:pci_core1.PciAdIn
AD[30] <= AD~33
AD[31] <= pcicore:pci_core1.PciAdIn
AD[31] <= AD~32
CBE_[0] => CBE_[0]~3.IN1
CBE_[1] => CBE_[1]~2.IN1
CBE_[2] => CBE_[2]~1.IN1
CBE_[3] => CBE_[3]~0.IN1
IDSEL => IDSEL~0.IN1
FRAME_ => FRAME_~0.IN1
DEVSEL_ <= DEVSEL_~0.DB_MAX_OUTPUT_PORT_TYPE
TRDY_ <= TRDY_~0.DB_MAX_OUTPUT_PORT_TYPE
IRDY_ => IRDY_~0.IN1
STOP_ <= STOP_~0.DB_MAX_OUTPUT_PORT_TYPE
PAR <= PAR~0.DB_MAX_OUTPUT_PORT_TYPE
INTA_ <= INTA_~0.DB_MAX_OUTPUT_PORT_TYPE
LocalInt_ => LocalInt_~0.IN1
LocalReset_ <= pcicore:pci_core1.LocalReset_
P0[0] <= P0~15
P0[1] <= P0~14
P0[2] <= P0~13
P0[3] <= P0~12
P0[4] <= P0~11
P0[5] <= P0~10
P0[6] <= P0~9
P0[7] <= P0~8
AL[0] <= pcicore:pci_core1.E8051Al
AL[1] <= pcicore:pci_core1.E8051Al
AL[2] <= pcicore:pci_core1.E8051Al
AL[3] <= pcicore:pci_core1.E8051Al
AL[4] <= pcicore:pci_core1.E8051Al
AL[5] <= pcicore:pci_core1.E8051Al
AL[6] <= pcicore:pci_core1.E8051Al
AL[7] <= pcicore:pci_core1.E8051Al
P2[0] <= pcicore:pci_core1.E8051P2
P2[1] <= pcicore:pci_core1.E8051P2
P2[2] <= pcicore:pci_core1.E8051P2
P2[3] <= pcicore:pci_core1.E8051P2
P2[4] <= pcicore:pci_core1.E8051P2
P2[5] <= pcicore:pci_core1.E8051P2
P2[6] <= pcicore:pci_core1.E8051P2
P2[7] <= pcicore:pci_core1.E8051P2
ALE <= pcicore:pci_core1.E8051Ale
WR_ <= pcicore:pci_core1.E8051Wr_
RD_ <= pcicore:pci_core1.E8051Rd_
IoWR_ <= <GND>
IoRD_ <= pcicore:pci_core1.E8051IoRd_
CS_LED <= <GND>
CS_SW <= pcicore:pci_core1.E8051IoRd_


|pci_top|pcicore:pci_core1
PciReset_ => PciCycleBeginRst_.IN1
PciReset_ => LocalReset_~0.IN1
PciReset_ => BUTTON_INT_CLEAR.IN0
PciReset_ => PciTrdy_~reg0.PRESET
PciReset_ => PciStop_~reg0.PRESET
PciReset_ => PciAdOutEnable~reg0.ACLR
PciReset_ => PciParOutEnable~reg0.ACLR
PciReset_ => PciDevselTrdyStopOutEnable~reg0.ACLR
PciReset_ => ConfigWriteEnable.ACLR
PciReset_ => ConfigDataOut[31].OUTPUTSELECT
PciReset_ => E8051Ale~reg0.PRESET
PciReset_ => E8051P0OutEnable~reg0.ACLR
PciReset_ => E8051Wr_~reg0.PRESET
PciReset_ => E8051Rd_~reg0.PRESET
PciReset_ => E8051IoWr_~reg0.PRESET
PciReset_ => E8051IoRd_~reg0.PRESET
PciReset_ => E8051P0DataAddressSelect.PRESET
PciReset_ => InnerIoWriteStrobe.PRESET
PciReset_ => P2LatchStrobe.ACLR
PciReset_ => ConfigDataOut[30].OUTPUTSELECT
PciReset_ => PciDevsel_~reg0.PRESET
PciReset_ => ConfigDataOut[29].OUTPUTSELECT
PciReset_ => ConfigDataOut[28].OUTPUTSELECT
PciReset_ => ConfigDataOut[27].OUTPUTSELECT
PciReset_ => ConfigDataOut[26].OUTPUTSELECT
PciReset_ => ConfigDataOut[25].OUTPUTSELECT
PciReset_ => ConfigDataOut[24].OUTPUTSELECT
PciReset_ => ConfigDataOut[23].OUTPUTSELECT
PciReset_ => ConfigDataOut[22].OUTPUTSELECT
PciReset_ => ConfigDataOut[21].OUTPUTSELECT
PciReset_ => ConfigDataOut[20].OUTPUTSELECT
PciReset_ => ConfigDataOut[19].OUTPUTSELECT
PciReset_ => ConfigDataOut[18].OUTPUTSELECT
PciReset_ => ConfigDataOut[17].OUTPUTSELECT
PciReset_ => ConfigDataOut[16].OUTPUTSELECT
PciReset_ => ConfigDataOut[15].OUTPUTSELECT
PciReset_ => ConfigDataOut[14].OUTPUTSELECT
PciReset_ => ConfigDataOut[13].OUTPUTSELECT
PciReset_ => ConfigDataOut[12].OUTPUTSELECT
PciReset_ => ConfigDataOut[11].OUTPUTSELECT
PciReset_ => ConfigDataOut[10].OUTPUTSELECT
PciReset_ => ConfigDataOut[9].OUTPUTSELECT
PciReset_ => ConfigDataOut[8].OUTPUTSELECT
PciReset_ => ConfigDataOut[7].OUTPUTSELECT
PciReset_ => ConfigDataOut[6].OUTPUTSELECT
PciReset_ => ConfigDataOut[5].OUTPUTSELECT
PciReset_ => ConfigDataOut[4].OUTPUTSELECT
PciReset_ => ConfigDataOut[3].OUTPUTSELECT
PciReset_ => ConfigDataOut[2].OUTPUTSELECT
PciReset_ => ConfigDataOut[1].OUTPUTSELECT
PciReset_ => ConfigDataOut[0].OUTPUTSELECT
PciReset_ => E8051Al[6]~reg0.ACLR
PciReset_ => E8051Al[5]~reg0.ACLR
PciReset_ => E8051Al[4]~reg0.ACLR
PciReset_ => E8051Al[3]~reg0.ACLR
PciReset_ => E8051Al[2]~reg0.ACLR
PciReset_ => E8051Al[1]~reg0.ACLR
PciReset_ => E8051Al[0]~reg0.ACLR
PciReset_ => E8051Al[7]~reg0.ACLR
PciReset_ => E8051P2[6]~reg0.ACLR
PciReset_ => E8051P2[5]~reg0.ACLR
PciReset_ => E8051P2[4]~reg0.ACLR
PciReset_ => E8051P2[3]~reg0.ACLR
PciReset_ => E8051P2[2]~reg0.ACLR
PciReset_ => E8051P2[1]~reg0.ACLR
PciReset_ => E8051P2[0]~reg0.ACLR
PciReset_ => E8051P2[7]~reg0.ACLR
PciReset_ => PciAdressReg[30].ACLR
PciReset_ => PciAdressReg[29].ACLR
PciReset_ => PciAdressReg[28].ACLR
PciReset_ => PciAdressReg[27].ACLR
PciReset_ => PciAdressReg[26].ACLR
PciReset_ => PciAdressReg[25].ACLR
PciReset_ => PciAdressReg[24].ACLR
PciReset_ => PciAdressReg[23].ACLR
PciReset_ => PciAdressReg[22].ACLR
PciReset_ => PciAdressReg[21].ACLR
PciReset_ => PciAdressReg[20].ACLR
PciReset_ => PciAdressReg[19].ACLR
PciReset_ => PciAdressReg[18].ACLR
PciReset_ => PciAdressReg[17].ACLR
PciReset_ => PciAdressReg[16].ACLR
PciReset_ => PciAdressReg[15].ACLR
PciReset_ => PciAdressReg[14].ACLR
PciReset_ => PciAdressReg[13].ACLR
PciReset_ => PciAdressReg[12].ACLR
PciReset_ => PciAdressReg[11].ACLR
PciReset_ => PciAdressReg[10].ACLR
PciReset_ => PciAdressReg[9].ACLR
PciReset_ => PciAdressReg[8].ACLR
PciReset_ => PciAdressReg[7].ACLR
PciReset_ => PciAdressReg[6].ACLR
PciReset_ => PciAdressReg[5].ACLR
PciReset_ => PciAdressReg[4].ACLR
PciReset_ => PciAdressReg[3].ACLR
PciReset_ => PciAdressReg[2].ACLR
PciReset_ => PciCbeReg[3].ACLR
PciReset_ => PciCbeReg[2].ACLR
PciReset_ => PciCbeReg[1].ACLR
PciReset_ => PciCbeReg[0].ACLR
PciReset_ => PciAdressReg[31].ACLR
PciReset_ => Com[0].ACLR
PciReset_ => BaseAddress0[31].PRESET
PciReset_ => BaseAddress0[30].PRESET
PciReset_ => BaseAddress0[29].PRESET
PciReset_ => BaseAddress0[28].PRESET
PciReset_ => BaseAddress0[27].PRESET
PciReset_ => BaseAddress0[26].PRESET
PciReset_ => BaseAddress0[25].PRESET
PciReset_ => BaseAddress0[24].PRESET
PciReset_ => BaseAddress0[23].PRESET
PciReset_ => BaseAddress0[22].PRESET
PciReset_ => BaseAddress0[21].PRESET
PciReset_ => BaseAddress0[20].PRESET
PciReset_ => BaseAddress0[19].PRESET
PciReset_ => BaseAddress0[18].PRESET
PciReset_ => BaseAddress0[17].PRESET
PciReset_ => BaseAddress0[16].PRESET
PciReset_ => BaseAddress0[15].PRESET
PciReset_ => BaseAddress0[14].PRESET
PciReset_ => BaseAddress0[13].PRESET
PciReset_ => BaseAddress0[12].PRESET
PciReset_ => BaseAddress0[11].PRESET
PciReset_ => BaseAddress0[10].PRESET
PciReset_ => BaseAddress0[9].PRESET
PciReset_ => BaseAddress0[8].PRESET
PciReset_ => BaseAddress0[7].PRESET
PciReset_ => BaseAddress0[6].PRESET
PciReset_ => BaseAddress0[5].PRESET
PciReset_ => BaseAddress0[4].PRESET
PciReset_ => BaseAddress1[31].PRESET
PciReset_ => BaseAddress1[30].PRESET
PciReset_ => BaseAddress1[29].PRESET
PciReset_ => BaseAddress1[28].PRESET
PciReset_ => BaseAddress1[27].PRESET
PciReset_ => BaseAddress1[26].PRESET
PciReset_ => BaseAddress1[25].PRESET
PciReset_ => BaseAddress1[24].PRESET
PciReset_ => BaseAddress1[23].PRESET
PciReset_ => BaseAddress1[22].PRESET
PciReset_ => BaseAddress1[21].PRESET
PciReset_ => BaseAddress1[20].PRESET
PciReset_ => BaseAddress1[19].PRESET
PciReset_ => BaseAddress1[18].PRESET
PciReset_ => InterruptLine[7].PRESET
PciReset_ => InterruptLine[6].PRESET
PciReset_ => InterruptLine[5].PRESET
PciReset_ => InterruptLine[4].PRESET
PciReset_ => InterruptLine[3].PRESET
PciReset_ => InterruptLine[2].PRESET
PciReset_ => InterruptLine[1].PRESET
PciReset_ => InterruptLine[0].PRESET
PciReset_ => Com[1].ACLR
PciReset_ => InnerIoReg[5].ACLR
PciReset_ => InnerIoReg[4].ACLR
PciReset_ => InnerIoReg[3].ACLR
PciReset_ => InnerIoReg[2].ACLR
PciReset_ => InnerIoReg[1].ACLR
PciReset_ => InnerIoReg[0].ACLR
PciReset_ => InnerIoReg[6].ACLR
PciReset_ => INT_SCAN_COUNTER[17].ACLR
PciReset_ => INT_SCAN_COUNTER[16].ACLR
PciReset_ => INT_SCAN_COUNTER[15].ACLR
PciReset_ => INT_SCAN_COUNTER[14].ACLR
PciReset_ => INT_SCAN_COUNTER[13].ACLR
PciReset_ => INT_SCAN_COUNTER[12].ACLR
PciReset_ => INT_SCAN_COUNTER[11].ACLR
PciReset_ => INT_SCAN_COUNTER[10].ACLR
PciReset_ => INT_SCAN_COUNTER[9].ACLR
PciReset_ => INT_SCAN_COUNTER[8].ACLR
PciReset_ => INT_SCAN_COUNTER[7].ACLR
PciReset_ => INT_SCAN_COUNTER[6].ACLR
PciReset_ => INT_SCAN_COUNTER[5].ACLR
PciReset_ => INT_SCAN_COUNTER[4].ACLR
PciReset_ => INT_SCAN_COUNTER[3].ACLR
PciReset_ => INT_SCAN_COUNTER[2].ACLR
PciReset_ => INT_SCAN_COUNTER[1].ACLR
PciReset_ => INT_SCAN_COUNTER[0].ACLR
PciReset_ => INT_SCAN_COUNTER[18].ACLR
PciReset_ => PciCycleBeginClear_.PRESET
PciReset_ => BUTTON_INT_REG.PRESET
PciReset_ => PciStateMachine~7.IN1
PciReset_ => PciAdOutSelect~7.IN1
PciClk => PciTrdy_~reg0.CLK
PciClk => PciStop_~reg0.CLK
PciClk => PciAdOutEnable~reg0.CLK
PciClk => PciParOutEnable~reg0.CLK
PciClk => PciDevselTrdyStopOutEnable~reg0.CLK
PciClk => ConfigWriteEnable.CLK
PciClk => E8051Ale~reg0.CLK
PciClk => E8051P0OutEnable~reg0.CLK
PciClk => E8051Wr_~reg0.CLK
PciClk => E8051Rd_~reg0.CLK
PciClk => E8051IoWr_~reg0.CLK
PciClk => E8051IoRd_~reg0.CLK
PciClk => E8051P0DataAddressSelect.CLK
PciClk => InnerIoWriteStrobe.CLK
PciClk => P2LatchStrobe.CLK
PciClk => PciCycleBeginClear_.CLK
PciClk => PciAdressReg[31].CLK
PciClk => PciAdressReg[30].CLK
PciClk => PciAdressReg[29].CLK
PciClk => PciAdressReg[28].CLK
PciClk => PciAdressReg[27].CLK
PciClk => PciAdressReg[26].CLK
PciClk => PciAdressReg[25].CLK
PciClk => PciAdressReg[24].CLK
PciClk => PciAdressReg[23].CLK
PciClk => PciAdressReg[22].CLK
PciClk => PciAdressReg[21].CLK
PciClk => PciAdressReg[20].CLK
PciClk => PciAdressReg[19].CLK
PciClk => PciAdressReg[18].CLK
PciClk => PciAdressReg[17].CLK
PciClk => PciAdressReg[16].CLK
PciClk => PciAdressReg[15].CLK
PciClk => PciAdressReg[14].CLK
PciClk => PciAdressReg[13].CLK
PciClk => PciAdressReg[12].CLK
PciClk => PciAdressReg[11].CLK
PciClk => PciAdressReg[10].CLK
PciClk => PciAdressReg[9].CLK
PciClk => PciAdressReg[8].CLK