📄 pci_top.tan.qmsg
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{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "pcicore:pci_core1\|PciAdressReg\[4\] pcicore:pci_core1\|E8051Al\[2\] CLK 3.0 ns " "Info: Found hold time violation between source pin or register \"pcicore:pci_core1\|PciAdressReg\[4\]\" and destination pin or register \"pcicore:pci_core1\|E8051Al\[2\]\" for clock \"CLK\" (Hold time is 3.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.700 ns + Largest " "Info: + Largest clock skew is 4.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 10.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.800 ns) 6.100 ns pcicore:pci_core1\|E8051Ale 2 REG LC1_B8 11 " "Info: 2: + IC(3.300 ns) + CELL(0.800 ns) = 6.100 ns; Loc. = LC1_B8; Fanout = 11; REG Node = 'pcicore:pci_core1\|E8051Ale'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { CLK pcicore:pci_core1|E8051Ale } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 160 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 10.000 ns pcicore:pci_core1\|E8051Al\[2\] 3 REG LC3_A11 1 " "Info: 3: + IC(3.900 ns) + CELL(0.000 ns) = 10.000 ns; Loc. = LC3_A11; Fanout = 1; REG Node = 'pcicore:pci_core1\|E8051Al\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 711 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 28.00 % ) " "Info: Total cell delay = 2.800 ns ( 28.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns ( 72.00 % ) " "Info: Total interconnect delay = 7.200 ns ( 72.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { CLK pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { CLK CLK~out pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } { 0.000ns 0.000ns 3.300ns 3.900ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns pcicore:pci_core1\|PciAdressReg\[4\] 2 REG LC4_A11 30 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A11; Fanout = 30; REG Node = 'pcicore:pci_core1\|PciAdressReg\[4\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { CLK pcicore:pci_core1|PciAdressReg[4] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 534 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciAdressReg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciAdressReg[4] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { CLK pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { CLK CLK~out pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } { 0.000ns 0.000ns 3.300ns 3.900ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciAdressReg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciAdressReg[4] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns - " "Info: - Micro clock to output delay of source is 0.800 ns" { } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 534 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns - Shortest register register " "Info: - Shortest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pcicore:pci_core1\|PciAdressReg\[4\] 1 REG LC4_A11 30 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A11; Fanout = 30; REG Node = 'pcicore:pci_core1\|PciAdressReg\[4\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pcicore:pci_core1|PciAdressReg[4] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 534 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 1.800 ns pcicore:pci_core1\|E8051Al\[2\] 2 REG LC3_A11 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 1.800 ns; Loc. = LC3_A11; Fanout = 1; REG Node = 'pcicore:pci_core1\|E8051Al\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { pcicore:pci_core1|PciAdressReg[4] pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 711 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 88.89 % ) " "Info: Total cell delay = 1.600 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 11.11 % ) " "Info: Total interconnect delay = 0.200 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { pcicore:pci_core1|PciAdressReg[4] pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { pcicore:pci_core1|PciAdressReg[4] pcicore:pci_core1|E8051Al[2] } { 0.000ns 0.200ns } { 0.000ns 1.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" { } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 711 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { CLK pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { CLK CLK~out pcicore:pci_core1|E8051Ale pcicore:pci_core1|E8051Al[2] } { 0.000ns 0.000ns 3.300ns 3.900ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciAdressReg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciAdressReg[4] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { pcicore:pci_core1|PciAdressReg[4] pcicore:pci_core1|E8051Al[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { pcicore:pci_core1|PciAdressReg[4] pcicore:pci_core1|E8051Al[2] } { 0.000ns 0.200ns } { 0.000ns 1.600ns } } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pcicore:pci_core1\|PciPar RESET_ CLK 23.200 ns register " "Info: tsu for register \"pcicore:pci_core1\|PciPar\" (data pin = \"RESET_\", clock pin = \"CLK\") is 23.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.800 ns + Longest pin register " "Info: + Longest pin to register delay is 26.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns RESET_ 1 PIN PIN_54 172 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 172; PIN Node = 'RESET_'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RESET_ } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(2.400 ns) 9.400 ns pcicore:pci_core1\|PciAdOut\[28\]~2619 2 COMB LC1_C17 33 " "Info: 2: + IC(5.000 ns) + CELL(2.400 ns) = 9.400 ns; Loc. = LC1_C17; Fanout = 33; COMB Node = 'pcicore:pci_core1\|PciAdOut\[28\]~2619'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { RESET_ pcicore:pci_core1|PciAdOut[28]~2619 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.400 ns) 15.200 ns pcicore:pci_core1\|PciAdOut\[26\]~2621 3 COMB LC6_A8 2 " "Info: 3: + IC(3.400 ns) + CELL(2.400 ns) = 15.200 ns; Loc. = LC6_A8; Fanout = 2; COMB Node = 'pcicore:pci_core1\|PciAdOut\[26\]~2621'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[26]~2621 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.400 ns) 18.800 ns pcicore:pci_core1\|ParReg~540 4 COMB LC3_A10 1 " "Info: 4: + IC(1.200 ns) + CELL(2.400 ns) = 18.800 ns; Loc. = LC3_A10; Fanout = 1; COMB Node = 'pcicore:pci_core1\|ParReg~540'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { pcicore:pci_core1|PciAdOut[26]~2621 pcicore:pci_core1|ParReg~540 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 214 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.400 ns) 24.200 ns pcicore:pci_core1\|ParReg~544 5 COMB LC4_B19 1 " "Info: 5: + IC(3.000 ns) + CELL(2.400 ns) = 24.200 ns; Loc. = LC4_B19; Fanout = 1; COMB Node = 'pcicore:pci_core1\|ParReg~544'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { pcicore:pci_core1|ParReg~540 pcicore:pci_core1|ParReg~544 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 214 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 26.800 ns pcicore:pci_core1\|PciPar 6 REG LC6_B17 1 " "Info: 6: + IC(1.000 ns) + CELL(1.600 ns) = 26.800 ns; Loc. = LC6_B17; Fanout = 1; REG Node = 'pcicore:pci_core1\|PciPar'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { pcicore:pci_core1|ParReg~544 pcicore:pci_core1|PciPar } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.200 ns ( 49.25 % ) " "Info: Total cell delay = 13.200 ns ( 49.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.600 ns ( 50.75 % ) " "Info: Total interconnect delay = 13.600 ns ( 50.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "26.800 ns" { RESET_ pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[26]~2621 pcicore:pci_core1|ParReg~540 pcicore:pci_core1|ParReg~544 pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "26.800 ns" { RESET_ RESET_~out pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[26]~2621 pcicore:pci_core1|ParReg~540 pcicore:pci_core1|ParReg~544 pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 5.000ns 3.400ns 1.200ns 3.000ns 1.000ns } { 0.000ns 2.000ns 2.400ns 2.400ns 2.400ns 2.400ns 1.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.700 ns + " "Info: + Micro setup delay of destination is 1.700 ns" { } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns pcicore:pci_core1\|PciPar 2 REG LC6_B17 1 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B17; Fanout = 1; REG Node = 'pcicore:pci_core1\|PciPar'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "26.800 ns" { RESET_ pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[26]~2621 pcicore:pci_core1|ParReg~540 pcicore:pci_core1|ParReg~544 pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "26.800 ns" { RESET_ RESET_~out pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[26]~2621 pcicore:pci_core1|ParReg~540 pcicore:pci_core1|ParReg~544 pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 5.000ns 3.400ns 1.200ns 3.000ns 1.000ns } { 0.000ns 2.000ns 2.400ns 2.400ns 2.400ns 2.400ns 1.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK AD\[0\] pcicore:pci_core1\|PciAdOutSelect.00 27.800 ns register " "Info: tco from clock \"CLK\" to destination pin \"AD\[0\]\" through register \"pcicore:pci_core1\|PciAdOutSelect.00\" is 27.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns pcicore:pci_core1\|PciAdOutSelect.00 2 REG LC6_B13 18 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B13; Fanout = 18; REG Node = 'pcicore:pci_core1\|PciAdOutSelect.00'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { CLK pcicore:pci_core1|PciAdOutSelect.00 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 195 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciAdOutSelect.00 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciAdOutSelect.00 } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" { } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 195 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.700 ns + Longest register pin " "Info: + Longest register to pin delay is 21.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pcicore:pci_core1\|PciAdOutSelect.00 1 REG LC6_B13 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B13; Fanout = 18; REG Node = 'pcicore:pci_core1\|PciAdOutSelect.00'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pcicore:pci_core1|PciAdOutSelect.00 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 195 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.200 ns) 4.500 ns pcicore:pci_core1\|PciAdOut\[28\]~2619 2 COMB LC1_C17 33 " "Info: 2: + IC(2.300 ns) + CELL(2.200 ns) = 4.500 ns; Loc. = LC1_C17; Fanout = 33; COMB Node = 'pcicore:pci_core1\|PciAdOut\[28\]~2619'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { pcicore:pci_core1|PciAdOutSelect.00 pcicore:pci_core1|PciAdOut[28]~2619 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.200 ns) 10.100 ns pcicore:pci_core1\|PciAdOut\[0\]~2647 3 COMB LC3_A8 2 " "Info: 3: + IC(3.400 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC3_A8; Fanout = 2; COMB Node = 'pcicore:pci_core1\|PciAdOut\[0\]~2647'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.400 ns) 15.700 ns pcicore:pci_core1\|PciAdOut\[0\]~2675 4 COMB LC5_B21 1 " "Info: 4: + IC(3.200 ns) + CELL(2.400 ns) = 15.700 ns; Loc. = LC5_B21; Fanout = 1; COMB Node = 'pcicore:pci_core1\|PciAdOut\[0\]~2675'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(4.800 ns) 21.700 ns AD\[0\] 5 PIN PIN_140 0 " "Info: 5: + IC(1.200 ns) + CELL(4.800 ns) = 21.700 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'AD\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.600 ns ( 53.46 % ) " "Info: Total cell delay = 11.600 ns ( 53.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.100 ns ( 46.54 % ) " "Info: Total interconnect delay = 10.100 ns ( 46.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.700 ns" { pcicore:pci_core1|PciAdOutSelect.00 pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.700 ns" { pcicore:pci_core1|PciAdOutSelect.00 pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } { 0.000ns 2.300ns 3.400ns 3.200ns 1.200ns } { 0.000ns 2.200ns 2.200ns 2.400ns 4.800ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciAdOutSelect.00 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciAdOutSelect.00 } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.700 ns" { pcicore:pci_core1|PciAdOutSelect.00 pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.700 ns" { pcicore:pci_core1|PciAdOutSelect.00 pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } { 0.000ns 2.300ns 3.400ns 3.200ns 1.200ns } { 0.000ns 2.200ns 2.200ns 2.400ns 4.800ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "RESET_ AD\[0\] 26.600 ns Longest " "Info: Longest tpd from source pin \"RESET_\" to destination pin \"AD\[0\]\" is 26.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns RESET_ 1 PIN PIN_54 172 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 172; PIN Node = 'RESET_'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RESET_ } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(2.400 ns) 9.400 ns pcicore:pci_core1\|PciAdOut\[28\]~2619 2 COMB LC1_C17 33 " "Info: 2: + IC(5.000 ns) + CELL(2.400 ns) = 9.400 ns; Loc. = LC1_C17; Fanout = 33; COMB Node = 'pcicore:pci_core1\|PciAdOut\[28\]~2619'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { RESET_ pcicore:pci_core1|PciAdOut[28]~2619 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.200 ns) 15.000 ns pcicore:pci_core1\|PciAdOut\[0\]~2647 3 COMB LC3_A8 2 " "Info: 3: + IC(3.400 ns) + CELL(2.200 ns) = 15.000 ns; Loc. = LC3_A8; Fanout = 2; COMB Node = 'pcicore:pci_core1\|PciAdOut\[0\]~2647'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.400 ns) 20.600 ns pcicore:pci_core1\|PciAdOut\[0\]~2675 4 COMB LC5_B21 1 " "Info: 4: + IC(3.200 ns) + CELL(2.400 ns) = 20.600 ns; Loc. = LC5_B21; Fanout = 1; COMB Node = 'pcicore:pci_core1\|PciAdOut\[0\]~2675'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(4.800 ns) 26.600 ns AD\[0\] 5 PIN PIN_140 0 " "Info: 5: + IC(1.200 ns) + CELL(4.800 ns) = 26.600 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'AD\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns ( 51.88 % ) " "Info: Total cell delay = 13.800 ns ( 51.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.800 ns ( 48.12 % ) " "Info: Total interconnect delay = 12.800 ns ( 48.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "26.600 ns" { RESET_ pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "26.600 ns" { RESET_ RESET_~out pcicore:pci_core1|PciAdOut[28]~2619 pcicore:pci_core1|PciAdOut[0]~2647 pcicore:pci_core1|PciAdOut[0]~2675 AD[0] } { 0.000ns 0.000ns 5.000ns 3.400ns 3.200ns 1.200ns } { 0.000ns 2.000ns 2.400ns 2.200ns 2.400ns 4.800ns } } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "pcicore:pci_core1\|InnerIoReg\[6\] AD\[6\] CLK 0.200 ns register " "Info: th for register \"pcicore:pci_core1\|InnerIoReg\[6\]\" (data pin = \"AD\[6\]\", clock pin = \"CLK\") is 0.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.800 ns) 6.100 ns pcicore:pci_core1\|InnerIoWriteStrobe 2 REG LC5_B24 10 " "Info: 2: + IC(3.300 ns) + CELL(0.800 ns) = 6.100 ns; Loc. = LC5_B24; Fanout = 10; REG Node = 'pcicore:pci_core1\|InnerIoWriteStrobe'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 222 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 7.400 ns pcicore:pci_core1\|InnerIoReg\[6\] 3 REG LC5_B16 1 " "Info: 3: + IC(1.300 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC5_B16; Fanout = 1; REG Node = 'pcicore:pci_core1\|InnerIoReg\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[6] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 37.84 % ) " "Info: Total cell delay = 2.800 ns ( 37.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 62.16 % ) " "Info: Total interconnect delay = 4.600 ns ( 62.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[6] } { 0.000ns 0.000ns 3.300ns 1.300ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" { } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AD\[6\] 1 PIN PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_132; Fanout = 1; PIN Node = 'AD\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AD[6] } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 5.000 ns AD\[6\]~25 2 COMB IOC_132 5 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 5.000 ns; Loc. = IOC_132; Fanout = 5; COMB Node = 'AD\[6\]~25'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.000 ns" { AD[6] AD[6]~25 } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.600 ns) 8.100 ns pcicore:pci_core1\|InnerIoReg\[6\] 3 REG LC5_B16 1 " "Info: 3: + IC(1.500 ns) + CELL(1.600 ns) = 8.100 ns; Loc. = LC5_B16; Fanout = 1; REG Node = 'pcicore:pci_core1\|InnerIoReg\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { AD[6]~25 pcicore:pci_core1|InnerIoReg[6] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns ( 81.48 % ) " "Info: Total cell delay = 6.600 ns ( 81.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 18.52 % ) " "Info: Total interconnect delay = 1.500 ns ( 18.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.100 ns" { AD[6] AD[6]~25 pcicore:pci_core1|InnerIoReg[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.100 ns" { AD[6] AD[6]~25 pcicore:pci_core1|InnerIoReg[6] } { 0.000ns 0.000ns 1.500ns } { 0.000ns 5.000ns 1.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[6] } { 0.000ns 0.000ns 3.300ns 1.300ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.100 ns" { AD[6] AD[6]~25 pcicore:pci_core1|InnerIoReg[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.100 ns" { AD[6] AD[6]~25 pcicore:pci_core1|InnerIoReg[6] } { 0.000ns 0.000ns 1.500ns } { 0.000ns 5.000ns 1.600ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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