pci_top.tan.qmsg

PIC 的ip 有用的着的拿去看看吧 对于开发pci总线会有很大帮助的

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "FRAME_ " "Info: Assuming node \"FRAME_\" is an undefined clock" {  } { { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 78 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FRAME_" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[18\] " "Info: Detected ripple clock \"pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[18\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pcicore:pci_core1\|BUTTON_INT_REG " "Info: Detected ripple clock \"pcicore:pci_core1\|BUTTON_INT_REG\" as buffer" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 674 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pcicore:pci_core1\|BUTTON_INT_REG" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pcicore:pci_core1\|P2LatchStrobe " "Info: Detected ripple clock \"pcicore:pci_core1\|P2LatchStrobe\" as buffer" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 218 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pcicore:pci_core1\|P2LatchStrobe" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pcicore:pci_core1\|E8051Ale " "Info: Detected ripple clock \"pcicore:pci_core1\|E8051Ale\" as buffer" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 160 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pcicore:pci_core1\|E8051Ale" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "pcicore:pci_core1\|InnerIoWriteStrobe " "Info: Detected ripple clock \"pcicore:pci_core1\|InnerIoWriteStrobe\" as buffer" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 222 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pcicore:pci_core1\|InnerIoWriteStrobe" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register pcicore:pci_core1\|InnerIoReg\[4\] register pcicore:pci_core1\|PciPar 29.76 MHz 33.6 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 29.76 MHz between source register \"pcicore:pci_core1\|InnerIoReg\[4\]\" and destination register \"pcicore:pci_core1\|PciPar\" (period= 33.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.200 ns + Longest register register " "Info: + Longest register to register delay is 12.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pcicore:pci_core1\|InnerIoReg\[4\] 1 REG LC2_B17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B17; Fanout = 1; REG Node = 'pcicore:pci_core1\|InnerIoReg\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pcicore:pci_core1|InnerIoReg[4] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 2.600 ns pcicore:pci_core1\|PciAdOut\[4\]~2657 2 COMB LC4_B17 2 " "Info: 2: + IC(0.200 ns) + CELL(2.400 ns) = 2.600 ns; Loc. = LC4_B17; Fanout = 2; COMB Node = 'pcicore:pci_core1\|PciAdOut\[4\]~2657'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { pcicore:pci_core1|InnerIoReg[4] pcicore:pci_core1|PciAdOut[4]~2657 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 5.200 ns pcicore:pci_core1\|PciAdOut\[4\]~2658 3 COMB LC5_B17 1 " "Info: 3: + IC(0.200 ns) + CELL(2.400 ns) = 5.200 ns; Loc. = LC5_B17; Fanout = 1; COMB Node = 'pcicore:pci_core1\|PciAdOut\[4\]~2658'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { pcicore:pci_core1|PciAdOut[4]~2657 pcicore:pci_core1|PciAdOut[4]~2658 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 7.800 ns pcicore:pci_core1\|ParReg~554 4 COMB LC7_B17 1 " "Info: 4: + IC(0.200 ns) + CELL(2.400 ns) = 7.800 ns; Loc. = LC7_B17; Fanout = 1; COMB Node = 'pcicore:pci_core1\|ParReg~554'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { pcicore:pci_core1|PciAdOut[4]~2658 pcicore:pci_core1|ParReg~554 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 10.400 ns pcicore:pci_core1\|ParReg~556 5 COMB LC8_B17 1 " "Info: 5: + IC(0.200 ns) + CELL(2.400 ns) = 10.400 ns; Loc. = LC8_B17; Fanout = 1; COMB Node = 'pcicore:pci_core1\|ParReg~556'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { pcicore:pci_core1|ParReg~554 pcicore:pci_core1|ParReg~556 } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 12.200 ns pcicore:pci_core1\|PciPar 6 REG LC6_B17 1 " "Info: 6: + IC(0.200 ns) + CELL(1.600 ns) = 12.200 ns; Loc. = LC6_B17; Fanout = 1; REG Node = 'pcicore:pci_core1\|PciPar'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { pcicore:pci_core1|ParReg~556 pcicore:pci_core1|PciPar } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns ( 91.80 % ) " "Info: Total cell delay = 11.200 ns ( 91.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 8.20 % ) " "Info: Total interconnect delay = 1.000 ns ( 8.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.200 ns" { pcicore:pci_core1|InnerIoReg[4] pcicore:pci_core1|PciAdOut[4]~2657 pcicore:pci_core1|PciAdOut[4]~2658 pcicore:pci_core1|ParReg~554 pcicore:pci_core1|ParReg~556 pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.200 ns" { pcicore:pci_core1|InnerIoReg[4] pcicore:pci_core1|PciAdOut[4]~2657 pcicore:pci_core1|PciAdOut[4]~2658 pcicore:pci_core1|ParReg~554 pcicore:pci_core1|ParReg~556 pcicore:pci_core1|PciPar } { 0.000ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns } { 0.000ns 2.400ns 2.400ns 2.400ns 2.400ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.100 ns - Smallest " "Info: - Smallest clock skew is -2.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns pcicore:pci_core1\|PciPar 2 REG LC6_B17 1 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B17; Fanout = 1; REG Node = 'pcicore:pci_core1\|PciPar'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 142 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 142; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.800 ns) 6.100 ns pcicore:pci_core1\|InnerIoWriteStrobe 2 REG LC5_B24 10 " "Info: 2: + IC(3.300 ns) + CELL(0.800 ns) = 6.100 ns; Loc. = LC5_B24; Fanout = 10; REG Node = 'pcicore:pci_core1\|InnerIoWriteStrobe'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 222 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 7.400 ns pcicore:pci_core1\|InnerIoReg\[4\] 3 REG LC2_B17 1 " "Info: 3: + IC(1.300 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC2_B17; Fanout = 1; REG Node = 'pcicore:pci_core1\|InnerIoReg\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } "NODE_NAME" } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 37.84 % ) " "Info: Total cell delay = 2.800 ns ( 37.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 62.16 % ) " "Info: Total interconnect delay = 4.600 ns ( 62.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } { 0.000ns 0.000ns 3.300ns 1.300ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } { 0.000ns 0.000ns 3.300ns 1.300ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.700 ns + " "Info: + Micro setup delay of destination is 1.700 ns" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 634 -1 0 } } { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 145 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.200 ns" { pcicore:pci_core1|InnerIoReg[4] pcicore:pci_core1|PciAdOut[4]~2657 pcicore:pci_core1|PciAdOut[4]~2658 pcicore:pci_core1|ParReg~554 pcicore:pci_core1|ParReg~556 pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.200 ns" { pcicore:pci_core1|InnerIoReg[4] pcicore:pci_core1|PciAdOut[4]~2657 pcicore:pci_core1|PciAdOut[4]~2658 pcicore:pci_core1|ParReg~554 pcicore:pci_core1|ParReg~556 pcicore:pci_core1|PciPar } { 0.000ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns } { 0.000ns 2.400ns 2.400ns 2.400ns 2.400ns 1.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK pcicore:pci_core1|PciPar } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out pcicore:pci_core1|PciPar } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out pcicore:pci_core1|InnerIoWriteStrobe pcicore:pci_core1|InnerIoReg[4] } { 0.000ns 0.000ns 3.300ns 1.300ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "FRAME_ " "Info: No valid register-to-register data paths exist for clock \"FRAME_\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 15 " "Warning: Circuit may not operate. Detected 15 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}