pci_top.map.qmsg

PIC 的ip 有用的着的拿去看看吧 对于开发pci总线会有很大帮助的

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Com pcicore.v(588) " "Warning (10235): Verilog HDL Always Construct warning at pcicore.v(588): variable \"Com\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 588 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "BaseAddress0 pcicore.v(590) " "Warning (10235): Verilog HDL Always Construct warning at pcicore.v(590): variable \"BaseAddress0\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 590 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "BaseAddress1 pcicore.v(591) " "Warning (10235): Verilog HDL Always Construct warning at pcicore.v(591): variable \"BaseAddress1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 591 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "InterruptLine pcicore.v(592) " "Warning (10235): Verilog HDL Always Construct warning at pcicore.v(592): variable \"InterruptLine\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 592 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 pcicore.v(668) " "Warning (10230): Verilog HDL assignment warning at pcicore.v(668): truncated value with size 32 to match size of target (19)" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 668 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "pcicore:pci_core1\|INT_SCAN_COUNTER\[0\]~0 19 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=19) from the following logic: \"pcicore:pci_core1\|INT_SCAN_COUNTER\[0\]~0\"" {  } { { "pcicore.v" "INT_SCAN_COUNTER\[0\]~0" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 665 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0 " "Info: Elaborated megafunction instantiation \"pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\|alt_counter_f10ke:wysi_counter pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0 " "Info: Elaborated megafunction instantiation \"pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 410 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0 " "Info: Instantiated megafunction \"pcicore:pci_core1\|lpm_counter:INT_SCAN_COUNTER_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 19 " "Info: Parameter \"LPM_WIDTH\" = \"19\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|pci_top\|pcicore:pci_core1\|PciStateMachine 16 " "Info: State machine \"\|pci_top\|pcicore:pci_core1\|PciStateMachine\" contains 16 states" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 206 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}