pci_top.map.qmsg

PIC 的ip 有用的着的拿去看看吧 对于开发pci总线会有很大帮助的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 10 11:41:47 2007 " "Info: Processing started: Tue Apr 10 11:41:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pci_top -c pci_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pci_top -c pci_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "PciParOutEnable pci_top.v(135) " "Warning (10236): Verilog HDL net warning at pci_top.v(135): created undeclared net \"PciParOutEnable\"" {  } { { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 135 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "E8051P0OutEnable pci_top.v(143) " "Warning (10236): Verilog HDL net warning at pci_top.v(143): created undeclared net \"E8051P0OutEnable\"" {  } { { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 143 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pci_top.v 1 1 " "Warning: Using design file pci_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 pci_top " "Info: Found entity 1: pci_top" {  } { { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 41 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pci_top " "Info: Elaborating entity \"pci_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "IoWR_ 0 pci_top.v(93) " "Warning (10030): Tied undriven net \"IoWR_\" at pci_top.v(93) to 0" {  } { { "pci_top.v" "" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 93 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pcicore.v 1 1 " "Warning: Using design file pcicore.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 pcicore " "Info: Found entity 1: pcicore" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 98 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pcicore pcicore:pci_core1 " "Info: Elaborating entity \"pcicore\" for hierarchy \"pcicore:pci_core1\"" {  } { { "pci_top.v" "pci_core1" { Text "D:/IP core/IFSPCI_IP/pci_top.v" 152 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "BUTTON_INT_ pcicore.v(569) " "Warning (10235): Verilog HDL Always Construct warning at pcicore.v(569): variable \"BUTTON_INT_\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 569 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "PciAdressReg pcicore.v(586) " "Warning (10235): Verilog HDL Always Construct warning at pcicore.v(586): variable \"PciAdressReg\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "pcicore.v" "" { Text "D:/IP core/IFSPCI_IP/pcicore.v" 586 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}