pci_top.v

PIC 的ip 有用的着的拿去看看吧 对于开发pci总线会有很大帮助的

/*123
**********************************************************************************
**********************************************************************************
//                  Interface Studio PCI IP Core
//		----Reference Design of 33MHz 32bit PCI Target Device		
//										
//										
//File name:pci_top.v
//Designor: duoduo
//Date:		15,Mar,2004
//Ver:		1.0
*********************************NOTE*********************************************
//            ALL COPY RIGHTS IS RESERVED BY INTERFACE STUDIO
**********************************************************************************
*/
//  Tis Reference Design is implementated using ALTERA's EPF10K10A device. It may 
//be implemented in other device by modification or not.
//  This design contains follow modules:
//	--pci_top.v
//  --pci_core.v

//This PCI Target IP Core support following features:
//	33MHz 32bit PCI and Intel 8051 back end interface 
//  Support one IO base address regions (16 bytes)
//	Support one memory base address regions (256K bytes)
//	Support one interrupt signal from the back end device to the PCI bus
//	Implementation of all required PCI configuration registers
//	Parity generation for all read cycles
//	Compliance with all PCI 2.2 requirements
//	A fully wave simulation is supplied use MAXPLUSII for verification

//This PCI Target IP Core does not support following features:
//	PERR and SERR 
//	Expansion ROM
//	Built-in Self Test (BIST)
//	Burst Access


`timescale 1ns/10ps

module pci_top
(
	CLK,			//PCI CLOCK
	RESET_,			//PCI RESET
	AD,			    //PCI AD BUS
	CBE_,			//PCI CBE BUS
	IDSEL,			//PCI IDSEL
	FRAME_,			//PCI FRAME
	DEVSEL_,		//PCI DEVSEL
	TRDY_,			//PCI TRDY
	IRDY_,			//PCI IRDY
	STOP_,			//PCI STOP
	PAR,			//PCI PAR
	INTA_,			//PCI INT

	LocalInt_,		//LOCAL INT INPUT
	LocalReset_,	//LOCAL RESET OUTPUT
	
	P0,			    //8051 P0 BUS
	AL,			    //8051 LOW 8 BIT ADDRESS LATCH OUTPUT
	P2,			    //8051 P2 BUS
	ALE,			//8051 ALE
	WR_,			//8051 WR
	RD_,			//8051 RD
	IoWR_,			//8051 EXPANDED IO WR 
	IoRD_,			//8051 EXPANDED IO RD 
	
	CS_LED,			//FOR EXPANDED IO--LED PERIPHERAL,74HC574 CLK
	CS_SW			//FOR EXPANDED IO--SWITCH PERIPHERAL, 74HC245 ENABLE
	
);	
//PCI interface signal
input	CLK;
input	RESET_;
inout	[31:0]	AD;
input	[3:0]	CBE_;
input	IDSEL;
input	FRAME_;
output	DEVSEL_;
output	TRDY_;
input	IRDY_;
output	STOP_;
output	PAR;
output	INTA_;	

//Local interface signal
inout	[7:0]	P0;
output  [7:0]	AL;
output	[7:0]	P2;
output	ALE;
output	WR_;
output	RD_;
output	IoWR_;
output	IoRD_;

output	CS_LED;
output	CS_SW;

input	LocalInt_;
output	LocalReset_;

//internal signal
wire	PciIntA_;
wire	PciIntAOutEnable;
wire	PciAdOutEnable;
wire	[31:0]	PciAdOut;
wire	PciDevselTrdyStopOutEnable;
wire	PciDevsel_;
wire	PciTrdy_;
wire	PciStop_;
wire	PciPar;

wire	[7:0]	E8051P0In;
wire	[7:0]	E8051P0Out;

////////////////////////////////
////////////////////////////////

pcicore pci_core1
(
	.PciReset_(RESET_),
	.PciClk(CLK),
	.PciFrame_(FRAME_),
	.PciIdsel(IDSEL),	
	.PciIrdy_(IRDY_), 
	.PciDevsel_(PciDevsel_), 
	.PciTrdy_(PciTrdy_),
	.PciStop_(PciStop_), 
	.PciPar(PciPar),  
	.PciCbe_(CBE_), 
	.PciAdIn(AD),
	.PciAdOut(PciAdOut),		
	.PciIntA_(PciIntA_),
	.PciAdOutEnable(PciAdOutEnable),
	.PciParOutEnable(PciParOutEnable),
	.PciDevselTrdyStopOutEnable(PciDevselTrdyStopOutEnable),
		
	.E8051Ale(ALE),
	.E8051Al(AL),
	.E8051P2(P2),
	.E8051P0In(E8051P0In),
	.E8051P0Out(E8051P0Out),
	.E8051P0OutEnable(E8051P0OutEnable),
	.E8051Wr_(WR_),
	.E8051Rd_(RD_),
	//.E8051IoWR_(IoWR_),
	.E8051IoRd_(IoRD_),
	
	.LocalInt_(LocalInt_),
	.LocalReset_(LocalReset_)

);	




assign	INTA_ = (PciIntA_ == 1'B0)? 1'B0:1'BZ;
assign  AD = (PciAdOutEnable == 1'B1) ? PciAdOut : 32'HZZZZZZZZ;
assign	DEVSEL_=(PciDevselTrdyStopOutEnable)? PciDevsel_ : 1'BZ;
assign	TRDY_ = (PciDevselTrdyStopOutEnable)? PciTrdy_ : 1'BZ;
assign	STOP_ = (PciDevselTrdyStopOutEnable)? PciStop_ : 1'BZ;
assign	PAR = (PciParOutEnable == 1'B1)? PciPar : 1'BZ;
assign	P0 = (E8051P0OutEnable == 1'B1)? E8051P0Out : 8'HZZ;
assign	E8051P0In = P0;
assign	CS_LED = IoWR_ ;
assign	CS_SW  = IoRD_ ;

endmodule