📄 pcicore.rpt
字号:
PciAdOut7 | 41 116 | E8051P0Out5
VCCIO | 42 115 | E8051Al5
VCCINT | 43 114 | N.C.
PciAdOut4 | 44 113 | N.C.
PciAdIn5 | 45 112 | PciAdIn16
PciAdOut5 | 46 111 | PciAdIn4
E8051P27 | 47 110 | VCCIO
GNDIO | 48 109 | VCCINT
GNDINT | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
P P P P E R G E E R E E P V P P P P E G E R R V V P P P G G E V L E E P P P G P R P P E R V P P R P P P
c c c c 8 E N 8 8 E 8 8 c C c c c c 8 N 8 E E C C c c c N N 8 C o 8 8 c c c N c E c c 8 E C c c E c c c
i i i i 0 S D 0 0 S 0 0 i C i i i i 0 D 0 S S C C i i i D D 0 C c 0 0 i i i D i S i i 0 S C i i S i i i
A A A A 5 E I 5 5 E 5 5 A I A C P A 5 I 5 E E I I R F I I I 5 I a 5 5 A A A I A E A A 5 E I A A E A A A
d d d d 1 R O 1 1 R 1 1 d O d b a d 1 O 1 R R N N e r r N N 1 O l 1 1 d d d O d R d d 1 R O d d R d d d
O O I I W V I I V R A O O e r I P P V V T T s a d T T P I P P I I I I V I I A V I I V I O I
u u n n r E o o E d l u u _ n 0 0 E E e m y 0 n 2 0 n n n n E n n l E n n E n u n
t t 1 1 _ D W R D _ 3 t t 0 1 I I D D t e _ O t 1 O 2 1 8 9 D 2 2 e D 3 3 D 1 t 2
2 1 9 7 r d 2 1 8 n n _ _ u _ u 5 4 6 0 0 3 7
6 6 _ _ 8 8 1 6 t t 0
6 7
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is not '5.0 V'-tolerant.
Device-Specific Information: d:\ip core\ifspci_ip\pcicore.rpt
pcicore
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
A3 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
A4 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
A5 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
A6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
A7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
A8 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
A9 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
A10 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 2/2 2/2 9/22( 40%)
A11 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
A12 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 12/22( 54%)
A13 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 5/22( 22%)
A14 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 16/22( 72%)
A16 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
A17 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
A18 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 12/22( 54%)
A19 7/ 8( 87%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 7/22( 31%)
A20 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 13/22( 59%)
A22 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
A24 8/ 8(100%) 8/ 8(100%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
B1 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 3/22( 13%)
B2 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
B3 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
B4 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
B5 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 1/2 2/22( 9%)
B6 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
B7 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
B8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 10/22( 45%)
B9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
B10 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 14/22( 63%)
B11 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
B12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 9/22( 40%)
B13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
B14 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 15/22( 68%)
B15 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 16/22( 72%)
B16 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 9/22( 40%)
B17 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 4/22( 18%)
B18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
B19 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
B20 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 16/22( 72%)
B21 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
B22 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
B23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
B24 5/ 8( 62%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
C1 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
C3 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 5/22( 22%)
C4 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
C6 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C7 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 1/22( 4%)
C8 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 4/22( 18%)
C9 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C12 6/ 8( 75%) 5/ 8( 62%) 2/ 8( 25%) 2/2 1/2 6/22( 27%)
C13 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C14 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 13/22( 59%)
C16 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
C17 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C18 8/ 8(100%) 6/ 8( 75%) 1/ 8( 12%) 1/2 1/2 9/22( 40%)
C19 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
C22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C23 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 115/128 ( 89%)
Total logic cells used: 393/576 ( 68%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.07/4 ( 76%)
Total fan-in: 1208/2304 ( 52%)
Total input pins required: 50
Total input I/O cell registers required: 0
Total output pins required: 71
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 393
Total flipflops required: 155
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 96/ 576 ( 16%)
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