📄 pcicore.rpt
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Project Information d:\ip core\ifspci_ip\pcicore.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/26/2007 22:28:50
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
pcicore EPF10K10AQC208-1 50 71 0 0 0 % 393 68 %
User Pins: 50 71 0
Project Information d:\ip core\ifspci_ip\pcicore.rpt
** FILE HIERARCHY **
|lpm_add_sub:2596|
|lpm_add_sub:2596|addcore:adder|
|lpm_add_sub:2596|altshift:result_ext_latency_ffs|
|lpm_add_sub:2596|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2596|altshift:oflow_ext_latency_ffs|
|lpm_xor:2597|
|lpm_xor:2598|
|lpm_xor:2599|
|lpm_xor:2600|
|lpm_xor:2601|
Device-Specific Information: d:\ip core\ifspci_ip\pcicore.rpt
pcicore
***** Logic for device 'pcicore' compiled without errors.
Device: EPF10K10AQC208-1
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information: d:\ip core\ifspci_ip\pcicore.rpt
pcicore
** ERROR SUMMARY **
Info: Chip 'pcicore' in device 'EPF10K10AQC208-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
E
P P P E P E P E E 8 E P
c c c P 8 c P 8 P P c 8 8 0 P P P P P P P 8 c
i i i c 0 E E P i c 0 E E c P R c i R 0 P P E E 0 5 E c R c R c c R c P E c E c R 0 i
A A A i 5 8 8 c A i 5 8 8 i c E i A E 5 c c 8 8 5 1 8 i E i E i i E i c 8 i 8 i E 5 A
d d d A 1 0 0 i d A 1 0 0 A i S A d S 1 G i P i V 0 0 1 P 0 A S A S A A S A i 0 A 0 A S 1 d
O O O d P 5 5 G I O d P 5 5 V d A E d O G E P N C c A C 5 5 V P 0 5 d E d G E d d E d V S 5 d 5 d E P O
u u u I 0 1 1 N n u I 0 1 1 C O d R I u N R 0 D b i d C 1 1 C 0 O 1 O R I N R I I R O C t 1 I 1 O R 0 u
t t t n I P P D t t n I A P C u I V n t D V I I e C I I P A C I u A u V n D V n n V u C o A n A u V I t
2 2 2 2 n 2 2 I A 1 1 n l 2 I t n E 2 2 I E n N _ l n N 2 l I n t l t E 1 I E 2 3 E t I p l 1 l t E n 3
9 3 5 1 0 2 3 O _ 7 3 4 4 0 O 1 7 D 3 1 O D 5 T 3 k 1 T 4 6 O 2 4 7 3 D 1 O D 4 1 D 2 O _ 0 5 2 8 D 3 1
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | GNDIO
VCCINT | 6 151 | GNDINT
N.C. | 7 150 | PciParOutEnable
N.C. | 8 149 | PciTrdy_
N.C. | 9 148 | PciDevselTrdyStopOutEnable
LocalReset_ | 10 147 | PciIdsel
PciCbe_2 | 11 146 | VCCIO
PciAdIn0 | 12 145 | VCCINT
PciCbe_1 | 13 144 | E8051P0Out1
N.C. | 14 143 | PciAdOutEnable
N.C. | 15 142 | PciDevsel_
PciAdIn29 | 16 141 | E8051P0OutEnable
E8051P0Out0 | 17 140 | N.C.
PciAdIn28 | 18 139 | N.C.
PciAdOut0 | 19 138 | VCCIO
GNDIO | 20 137 | VCCINT
GNDINT | 21 136 | E8051P25
VCCIO | 22 135 | PciAdOut14
VCCINT | 23 134 | PciAdIn20
PciAdOut11 | 24 133 | PciAdOut12
PciAdOut22 | 25 132 | PciAdIn22
PciAdOut19 | 26 131 | PciAdOut9
PciAdOut13 | 27 EPF10K10AQC208-1 130 | GNDIO
PciAdOut27 | 28 129 | GNDINT
PciAdIn12 | 29 128 | PciAdOut10
PciAdOut24 | 30 127 | PciAdOut15
PciAdOut20 | 31 126 | N.C.
GNDIO | 32 125 | N.C.
GNDINT | 33 124 | GNDIO
VCCIO | 34 123 | GNDINT
VCCINT | 35 122 | E8051P0Out2
N.C. | 36 121 | PciAdIn6
N.C. | 37 120 | E8051P0Out3
E8051P26 | 38 119 | E8051Al1
E8051P0In7 | 39 118 | VCCIO
PciAdOut6 | 40 117 | VCCINT
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