📄 pci_top.rpt
字号:
49 - - - 14 TRI 0 1 0 1 P00
48 - - - 15 TRI 0 1 0 1 P01
47 - - - 16 TRI 0 1 0 1 P02
46 - - - 17 TRI 0 1 0 1 P03
44 - - - 18 TRI 0 1 0 1 P04
43 - - - 18 TRI 0 1 0 1 P05
42 - - - 19 TRI 0 1 0 1 P06
41 - - - 20 TRI 0 1 0 1 P07
32 - - C -- FF 0 1 0 0 P20
31 - - C -- FF 0 1 0 0 P21
30 - - C -- FF 0 1 0 0 P22
29 - - C -- FF 0 1 0 0 P23
28 - - C -- FF 0 1 0 0 P24
27 - - C -- FF 0 1 0 0 P25
26 - - C -- FF 0 1 0 0 P26
23 - - B -- FF 0 1 0 0 P27
38 - - - 22 OUTPUT 0 1 0 0 RD_
95 - - A -- TRI 0 1 0 0 STOP_
91 - - B -- TRI 0 1 0 0 TRDY_
39 - - - 21 OUTPUT 0 1 0 0 WR_
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt
pci_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 22 SOFT s r 0 1 1 0 ALE~fit~in1
- 2 - A 12 AND2 0 4 0 4 |pcicore:pci_core1|lpm_add_sub:2596|addcore:adder0|:129
- 1 - A 12 AND2 0 2 0 2 |pcicore:pci_core1|lpm_add_sub:2596|addcore:adder0|:133
- 1 - A 05 AND2 0 4 0 4 |pcicore:pci_core1|lpm_add_sub:2596|addcore:adder1|:125
- 2 - A 03 AND2 0 4 0 4 |pcicore:pci_core1|lpm_add_sub:2596|addcore:adder1|:137
- 5 - A 05 LCELL 0 4 0 4 |pcicore:pci_core1|lpm_add_sub:2596|look_add:look_aheader|gpc0
- 4 - A 23 AND2 0 3 0 2 |pcicore:pci_core1|lpm_add_sub:2596|look_add:look_aheader|:45
- 7 - B 08 AND2 s 0 2 0 1 |pcicore:pci_core1|~122~1
- 8 - B 08 AND2 s 1 3 0 1 |pcicore:pci_core1|~122~2
- 2 - B 11 AND2 0 4 0 4 |pcicore:pci_core1|:122
- 8 - B 06 OR2 s ! 4 0 0 1 |pcicore:pci_core1|~154~1
- 8 - B 10 OR2 s ! 1 3 0 1 |pcicore:pci_core1|~154~2
- 3 - B 10 OR2 ! 0 4 0 2 |pcicore:pci_core1|:154
- 3 - B 05 DFFE + ! 0 1 0 1 |pcicore:pci_core1|PciCycleBeginClear_ (|pcicore:pci_core1|:163)
- 6 - B 05 AND2 1 1 0 1 |pcicore:pci_core1|:164
- 7 - B 03 AND2 s 0 3 0 1 |pcicore:pci_core1|PciCycleBegin~1 (|pcicore:pci_core1|~167~1)
- 4 - B 05 DFFE 1 1 0 2 |pcicore:pci_core1|PciCycleBegin (|pcicore:pci_core1|:167)
- 8 - B 02 AND2 1 1 0 34 |pcicore:pci_core1|:187
- 7 - C 11 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg31 (|pcicore:pci_core1|:195)
- 6 - C 14 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg30 (|pcicore:pci_core1|:196)
- 3 - C 09 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg29 (|pcicore:pci_core1|:197)
- 1 - C 10 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg28 (|pcicore:pci_core1|:198)
- 5 - C 07 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg27 (|pcicore:pci_core1|:199)
- 8 - C 08 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg26 (|pcicore:pci_core1|:200)
- 6 - C 06 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg25 (|pcicore:pci_core1|:201)
- 8 - C 05 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg24 (|pcicore:pci_core1|:202)
- 6 - C 24 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg23 (|pcicore:pci_core1|:203)
- 3 - C 22 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg22 (|pcicore:pci_core1|:204)
- 3 - C 14 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg21 (|pcicore:pci_core1|:205)
- 6 - C 20 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg20 (|pcicore:pci_core1|:206)
- 3 - C 13 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg19 (|pcicore:pci_core1|:207)
- 6 - C 23 DFFE + 0 2 0 2 |pcicore:pci_core1|PciAdressReg18 (|pcicore:pci_core1|:208)
- 7 - C 13 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg17 (|pcicore:pci_core1|:209)
- 4 - C 04 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg16 (|pcicore:pci_core1|:210)
- 2 - A 01 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg15 (|pcicore:pci_core1|:211)
- 3 - A 01 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg14 (|pcicore:pci_core1|:212)
- 4 - A 09 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg13 (|pcicore:pci_core1|:213)
- 5 - A 09 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg12 (|pcicore:pci_core1|:214)
- 6 - C 13 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg11 (|pcicore:pci_core1|:215)
- 7 - B 10 DFFE + 0 2 1 1 |pcicore:pci_core1|PciAdressReg10 (|pcicore:pci_core1|:216)
- 3 - A 10 DFFE + 0 2 1 2 |pcicore:pci_core1|PciAdressReg9 (|pcicore:pci_core1|:217)
- 6 - B 10 DFFE + 0 2 1 2 |pcicore:pci_core1|PciAdressReg8 (|pcicore:pci_core1|:218)
- 7 - A 20 DFFE + 0 2 1 5 |pcicore:pci_core1|PciAdressReg7 (|pcicore:pci_core1|:219)
- 4 - A 18 DFFE + 0 2 1 5 |pcicore:pci_core1|PciAdressReg6 (|pcicore:pci_core1|:220)
- 2 - A 18 DFFE + 0 2 1 5 |pcicore:pci_core1|PciAdressReg5 (|pcicore:pci_core1|:221)
- 3 - A 18 DFFE + 0 2 1 30 |pcicore:pci_core1|PciAdressReg4 (|pcicore:pci_core1|:222)
- 4 - B 20 DFFE + 0 2 1 14 |pcicore:pci_core1|PciAdressReg3 (|pcicore:pci_core1|:223)
- 5 - B 19 DFFE + 0 2 1 26 |pcicore:pci_core1|PciAdressReg2 (|pcicore:pci_core1|:224)
- 6 - C 05 AND2 0 3 0 57 |pcicore:pci_core1|:277
- 1 - B 03 OR2 s 0 4 0 2 |pcicore:pci_core1|~301~1
- 6 - B 03 AND2 s 0 2 0 1 |pcicore:pci_core1|~301~2
- 4 - B 03 AND2 s 0 2 0 1 |pcicore:pci_core1|~302~1
- 5 - B 08 AND2 s 1 2 0 1 |pcicore:pci_core1|~303~1
- 6 - B 08 AND2 s 0 3 0 1 |pcicore:pci_core1|~303~2
- 1 - B 08 AND2 0 4 0 2 |pcicore:pci_core1|:303
- 6 - B 06 DFFE + 1 1 0 5 |pcicore:pci_core1|PciCbeReg3 (|pcicore:pci_core1|:311)
- 1 - B 06 DFFE + 1 1 0 5 |pcicore:pci_core1|PciCbeReg2 (|pcicore:pci_core1|:312)
- 7 - B 06 DFFE + 1 1 0 5 |pcicore:pci_core1|PciCbeReg1 (|pcicore:pci_core1|:313)
- 5 - B 06 DFFE + 1 1 0 11 |pcicore:pci_core1|PciCbeReg0 (|pcicore:pci_core1|:314)
- 3 - B 08 AND2 s 0 3 0 2 |pcicore:pci_core1|~319~1
- 4 - B 01 AND2 0 4 0 3 |pcicore:pci_core1|:333
- 2 - B 08 DFFE + 0 3 0 52 |pcicore:pci_core1|ConfigWriteEnable (|pcicore:pci_core1|:344)
- 3 - B 03 DFFE + 0 4 0 4 |pcicore:pci_core1|Com1 (|pcicore:pci_core1|:348)
- 5 - B 03 DFFE + 0 4 0 3 |pcicore:pci_core1|Com0 (|pcicore:pci_core1|:349)
- 7 - B 04 AND2 0 4 0 1 |pcicore:pci_core1|:417
- 5 - B 01 AND2 0 4 0 8 |pcicore:pci_core1|:470
- 5 - C 11 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~619~1
- 7 - C 12 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~620~1
- 5 - C 09 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~621~1
- 6 - C 10 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~622~1
- 7 - C 07 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~623~1
- 5 - C 01 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~624~1
- 2 - C 01 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~625~1
- 7 - C 05 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~626~1
- 7 - C 14 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~627~1
- 6 - C 22 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~628~1
- 8 - C 14 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~629~1
- 4 - C 15 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~630~1
- 7 - C 18 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~631~1
- 4 - C 23 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~632~1
- 6 - C 04 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~633~1
- 5 - C 04 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~634~1
- 7 - A 01 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~635~1
- 5 - A 01 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~636~1
- 7 - A 09 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~637~1
- 3 - A 09 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~638~1
- 8 - C 01 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~639~1
- 2 - A 07 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~640~1
- 1 - A 10 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~641~1
- 2 - B 10 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~642~1
- 5 - A 15 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~643~1
- 6 - A 06 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~644~1
- 1 - C 15 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~645~1
- 5 - A 17 OR2 s ! 0 4 0 1 |pcicore:pci_core1|~646~1
- 3 - C 11 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress031 (|pcicore:pci_core1|:677)
- 8 - C 12 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress030 (|pcicore:pci_core1|:678)
- 6 - C 09 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress029 (|pcicore:pci_core1|:679)
- 2 - C 10 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress028 (|pcicore:pci_core1|:680)
- 1 - C 07 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress027 (|pcicore:pci_core1|:681)
- 4 - C 01 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress026 (|pcicore:pci_core1|:682)
- 3 - C 01 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress025 (|pcicore:pci_core1|:683)
- 4 - C 05 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress024 (|pcicore:pci_core1|:684)
- 1 - C 14 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress023 (|pcicore:pci_core1|:685)
- 4 - C 22 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress022 (|pcicore:pci_core1|:686)
- 5 - C 14 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress021 (|pcicore:pci_core1|:687)
- 8 - C 15 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress020 (|pcicore:pci_core1|:688)
- 8 - C 18 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress019 (|pcicore:pci_core1|:689)
- 8 - C 23 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress018 (|pcicore:pci_core1|:690)
- 8 - C 04 DFFE + ! 0 4 0 4 |pcicore:pci_core1|BaseAddress017 (|pcicore:pci_core1|:691)
- 1 - C 04 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress016 (|pcicore:pci_core1|:692)
- 6 - A 01 DFFE + ! 0 4 0 4 |pcicore:pci_core1|BaseAddress015 (|pcicore:pci_core1|:693)
- 1 - A 01 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress014 (|pcicore:pci_core1|:694)
- 8 - A 09 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress013 (|pcicore:pci_core1|:695)
- 1 - A 09 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress012 (|pcicore:pci_core1|:696)
- 6 - C 01 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress011 (|pcicore:pci_core1|:697)
- 6 - A 07 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress010 (|pcicore:pci_core1|:698)
- 2 - A 10 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress09 (|pcicore:pci_core1|:699)
- 5 - B 10 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress08 (|pcicore:pci_core1|:700)
- 4 - A 15 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress07 (|pcicore:pci_core1|:701)
- 8 - A 06 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress06 (|pcicore:pci_core1|:702)
- 6 - C 15 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress05 (|pcicore:pci_core1|:703)
- 1 - A 17 DFFE + ! 0 4 0 3 |pcicore:pci_core1|BaseAddress04 (|pcicore:pci_core1|:704)
- 2 - C 12 OR2 s 0 4 0 1 |pcicore:pci_core1|~817~1
- 7 - C 09 OR2 s 0 4 0 1 |pcicore:pci_core1|~817~2
- 3 - C 08 OR2 s 0 4 0 1 |pcicore:pci_core1|~817~3
- 7 - C 06 OR2 s 0 4 0 1 |pcicore:pci_core1|~817~4
- 2 - C 02 AND2 s 0 4 0 1 |pcicore:pci_core1|~817~5
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