📄 pci_top.rpt
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Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.45/4 ( 86%)
Total fan-in: 1330/2304 ( 57%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 29
Total output I/O cell registers required: 16
Total buried I/O cell registers required: 0
Total bidirectional pins required: 40
Total reserved pins required 12
Total logic cells required: 385
Total flipflops required: 141
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Logic cells inserted for fitting: 1
Synthesized logic cells: 136/ 576 ( 23%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 4 0 8 8 7 0 8 5 0 7 0 1 0 8 8 8 6 8 3 0 8 7 8 120/0
B: 8 2 8 8 8 8 6 8 7 8 8 8 0 1 0 0 0 7 0 8 5 8 5 2 0 123/0
C: 8 4 5 8 8 8 7 8 7 7 7 8 0 3 8 6 2 0 8 0 8 0 7 7 8 142/0
Total: 24 6 17 16 24 24 20 16 22 20 15 23 0 5 8 14 10 15 14 16 16 8 20 16 16 385/0
Device-Specific Information: h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt
pci_top
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
140 - - - 21 BIDIR 0 1 0 5 AD0
138 - - - 20 BIDIR 0 1 0 5 AD1
137 - - - 19 BIDIR 0 1 0 4 AD2
136 - - - 19 BIDIR 0 1 0 4 AD3
135 - - - 18 BIDIR 0 1 0 5 AD4
133 - - - 17 BIDIR 0 1 0 5 AD5
132 - - - 16 BIDIR 0 1 0 5 AD6
131 - - - 15 BIDIR 0 1 0 5 AD7
121 - - - 10 BIDIR 0 1 0 3 AD8
120 - - - 09 BIDIR 0 1 0 3 AD9
119 - - - 08 BIDIR 0 1 0 3 AD10
118 - - - 07 BIDIR 0 1 0 2 AD11
117 - - - 06 BIDIR 0 1 0 2 AD12
101 - - A -- BIDIR 0 1 0 2 AD13
100 - - A -- BIDIR 0 1 0 2 AD14
99 - - A -- BIDIR 0 1 0 2 AD15
87 - - B -- BIDIR 0 1 0 2 AD16
86 - - B -- BIDIR 0 1 0 2 AD17
83 - - C -- BIDIR 0 1 0 3 AD18
82 - - C -- BIDIR 0 1 0 3 AD19
81 - - C -- BIDIR 0 1 0 3 AD20
80 - - C -- BIDIR 0 1 0 3 AD21
79 - - C -- BIDIR 0 1 0 3 AD22
78 - - C -- BIDIR 0 1 0 3 AD23
70 - - - 05 BIDIR 0 1 0 3 AD24
69 - - - 06 BIDIR 0 1 0 3 AD25
68 - - - 07 BIDIR 0 1 0 3 AD26
67 - - - 08 BIDIR 0 1 0 3 AD27
65 - - - 09 BIDIR 0 1 0 3 AD28
64 - - - 10 BIDIR 0 1 0 3 AD29
63 - - - 11 BIDIR 0 1 0 3 AD30
62 - - - 11 BIDIR 0 1 0 3 AD31
130 - - - 14 INPUT 0 0 0 3 CBE_0
98 - - A -- INPUT 0 0 0 4 CBE_1
88 - - B -- INPUT 0 0 0 5 CBE_2
72 - - - 04 INPUT 0 0 0 4 CBE_3
55 - - - -- INPUT G 0 0 0 0 CLK
89 - - B -- INPUT 0 0 0 8 FRAME_
73 - - - 02 INPUT 0 0 0 2 IDSEL
90 - - B -- INPUT 0 0 0 6 IRDY_
22 - - B -- INPUT 0 0 0 1 LocalInt_
49 - - - 14 BIDIR 0 1 0 1 P00
48 - - - 15 BIDIR 0 1 0 1 P01
47 - - - 16 BIDIR 0 1 0 1 P02
46 - - - 17 BIDIR 0 1 0 1 P03
44 - - - 18 BIDIR 0 1 0 1 P04
43 - - - 18 BIDIR 0 1 0 1 P05
42 - - - 19 BIDIR 0 1 0 1 P06
41 - - - 20 BIDIR 0 1 0 1 P07
54 - - - -- INPUT G 0 0 0 4 RESET_
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt
pci_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
140 - - - 21 TRI 0 1 0 5 AD0
138 - - - 20 TRI 0 1 0 5 AD1
137 - - - 19 TRI 0 1 0 4 AD2
136 - - - 19 TRI 0 1 0 4 AD3
135 - - - 18 TRI 0 1 0 5 AD4
133 - - - 17 TRI 0 1 0 5 AD5
132 - - - 16 TRI 0 1 0 5 AD6
131 - - - 15 TRI 0 1 0 5 AD7
121 - - - 10 TRI 0 1 0 3 AD8
120 - - - 09 TRI 0 1 0 3 AD9
119 - - - 08 TRI 0 1 0 3 AD10
118 - - - 07 TRI 0 1 0 2 AD11
117 - - - 06 TRI 0 1 0 2 AD12
101 - - A -- TRI 0 1 0 2 AD13
100 - - A -- TRI 0 1 0 2 AD14
99 - - A -- TRI 0 1 0 2 AD15
87 - - B -- TRI 0 1 0 2 AD16
86 - - B -- TRI 0 1 0 2 AD17
83 - - C -- TRI 0 1 0 3 AD18
82 - - C -- TRI 0 1 0 3 AD19
81 - - C -- TRI 0 1 0 3 AD20
80 - - C -- TRI 0 1 0 3 AD21
79 - - C -- TRI 0 1 0 3 AD22
78 - - C -- TRI 0 1 0 3 AD23
70 - - - 05 TRI 0 1 0 3 AD24
69 - - - 06 TRI 0 1 0 3 AD25
68 - - - 07 TRI 0 1 0 3 AD26
67 - - - 08 TRI 0 1 0 3 AD27
65 - - - 09 TRI 0 1 0 3 AD28
64 - - - 10 TRI 0 1 0 3 AD29
63 - - - 11 TRI 0 1 0 3 AD30
62 - - - 11 TRI 0 1 0 3 AD31
33 - - C -- OUTPUT 0 1 0 0 ALE
21 - - B -- FF 0 1 0 0 AL0
20 - - B -- FF 0 1 0 0 AL1
19 - - B -- FF 0 1 0 0 AL2
18 - - B -- FF 0 1 0 0 AL3
17 - - B -- FF 0 1 0 0 AL4
13 - - A -- FF 0 1 0 0 AL5
12 - - A -- FF 0 1 0 0 AL6
10 - - A -- FF 0 1 0 0 AL7
128 - - - 13 OUTPUT 0 1 0 0 CS_LED
122 - - - 12 OUTPUT 0 1 0 0 CS_SW
92 - - B -- TRI 0 1 0 0 DEVSEL_
51 - - - 13 TRI 0 0 0 0 INTA_
36 - - - 24 OUTPUT 0 1 0 0 IoRD_
37 - - - 23 OUTPUT 0 1 0 0 IoWR_
7 - - A -- OUTPUT 0 1 0 0 LocalReset_
97 - - A -- TRI 0 1 0 0 PAR
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