📄 pci_top.rpt
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User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
C G G G G V + + + + + + +
G V C G S N N N N C C D V D D D D D D
+ + + N C B N _ D D D D C S A A A A C A A A A A A
n + n n A D A A A A C A A A E D L I I I I I _ A A D D D T C T T T T T T
C C W R D I D D D D I D D D _ I E N N N N N S D D 1 1 1 A I A A A A A A
S S S S 0 O 1 2 3 4 O 5 6 7 0 O D T T T T T W 8 9 0 1 2 7 O 6 5 4 3 2 1
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
LocalReset_ | 7 102 | RESERVED
RESERVED | 8 101 | AD13
RESERVED | 9 100 | AD14
AL7 | 10 99 | AD15
*RDYnBUSY | 11 98 | CBE_1
AL6 | 12 97 | PAR
AL5 | 13 96 | RESERVED
RESERVED | 14 95 | STOP_
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
AL4 | 17 92 | DEVSEL_
AL3 | 18 91 | TRDY_
AL2 | 19 EPF10K10ATC144-3 90 | IRDY_
AL1 | 20 89 | FRAME_
AL0 | 21 88 | CBE_2
LocalInt_ | 22 87 | AD16
P27 | 23 86 | AD17
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
P26 | 26 83 | AD18
P25 | 27 82 | AD19
P24 | 28 81 | AD20
P23 | 29 80 | AD21
P22 | 30 79 | AD22
P21 | 31 78 | AD23
P20 | 32 77 | ^MSEL0
ALE | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
IoRD_ | 36 73 | IDSEL
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
I R W G P P P P V P P P P G I V V R C G G G R R V A A A A G A A A A V C
o D R N 0 0 0 0 C 0 0 0 0 N N C C E L N N N E E C D D D D N D D D D C B
W _ _ D 7 6 5 4 C 3 2 1 0 D T C C S K D D D S S C 3 3 2 2 D 2 2 2 2 C E
R I I I A I I E I I I E E I 1 0 9 8 I 7 6 5 4 I _
_ O O O _ N N T N N N R R O O O 3
T T _ T T T V V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is not '5.0 V'-tolerant.
Device-Specific Information: h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt
pci_top
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
A3 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
A5 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
A6 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 14/22( 63%)
A7 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
A9 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
A10 5/ 8( 62%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 9/22( 40%)
A12 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 0/22( 0%)
A13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 13/22( 59%)
A16 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 14/22( 63%)
A17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 14/22( 63%)
A18 6/ 8( 75%) 7/ 8( 87%) 3/ 8( 37%) 1/2 1/2 7/22( 31%)
A19 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 17/22( 77%)
A20 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 6/22( 27%)
A22 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 16/22( 72%)
A23 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 2/2 1/2 2/22( 9%)
A24 8/ 8(100%) 6/ 8( 75%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
B1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
B2 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B3 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 12/22( 54%)
B4 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
B5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 2/2 7/22( 31%)
B6 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 9/22( 40%)
B7 6/ 8( 75%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 7/22( 31%)
B8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
B9 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 9/22( 40%)
B10 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 17/22( 77%)
B11 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
B12 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
B13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 3/22( 13%)
B17 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
B19 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 2/2 1/2 11/22( 50%)
B20 5/ 8( 62%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 9/22( 40%)
B21 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
B22 5/ 8( 62%) 3/ 8( 37%) 0/ 8( 0%) 1/2 1/2 8/22( 36%)
B23 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 4/22( 18%)
C1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
C2 4/ 8( 50%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 13/22( 59%)
C3 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 14/22( 63%)
C4 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
C5 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 1/2 9/22( 40%)
C6 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 15/22( 68%)
C7 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
C8 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 15/22( 68%)
C9 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 14/22( 63%)
C10 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
C11 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
C12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
C13 3/ 8( 37%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
C14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
C15 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
C16 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
C18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
C20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 14/22( 63%)
C22 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
C23 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
C24 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 89/96 ( 92%)
Total logic cells used: 385/576 ( 66%)
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