code.tan.qmsg

有关键盘接口的程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk s_out\[2\] s_out\[2\]\$latch 17.017 ns register " "Info: tco from clock \"clk\" to destination pin \"s_out\[2\]\" through register \"s_out\[2\]\$latch\" is 17.017 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.607 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns state.su_open 2 REG LC_X10_Y6_N7 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y6_N7; Fanout = 7; REG Node = 'state.su_open'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.032 ns" { clk state.su_open } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.955 ns) + CELL(0.511 ns) 5.661 ns Selector26~177 3 COMB LC_X10_Y6_N2 7 " "Info: 3: + IC(0.955 ns) + CELL(0.511 ns) = 5.661 ns; Loc. = LC_X10_Y6_N2; Fanout = 7; COMB Node = 'Selector26~177'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.466 ns" { state.su_open Selector26~177 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.746 ns) + CELL(0.200 ns) 11.607 ns s_out\[2\]\$latch 4 REG LC_X12_Y6_N4 1 " "Info: 4: + IC(5.746 ns) + CELL(0.200 ns) = 11.607 ns; Loc. = LC_X12_Y6_N4; Fanout = 1; REG Node = 's_out\[2\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.946 ns" { Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.168 ns ( 27.29 % ) " "Info: Total cell delay = 3.168 ns ( 27.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.439 ns ( 72.71 % ) " "Info: Total interconnect delay = 8.439 ns ( 72.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.607 ns" { clk state.su_open Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.607 ns" { clk clk~combout state.su_open Selector26~177 s_out[2]$latch } { 0.000ns 0.000ns 1.738ns 0.955ns 5.746ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.410 ns + Longest register pin " "Info: + Longest register to pin delay is 5.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s_out\[2\]\$latch 1 REG LC_X12_Y6_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y6_N4; Fanout = 1; REG Node = 's_out\[2\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { s_out[2]$latch } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.088 ns) + CELL(2.322 ns) 5.410 ns s_out\[2\] 2 PIN PIN_23 0 " "Info: 2: + IC(3.088 ns) + CELL(2.322 ns) = 5.410 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 's_out\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.410 ns" { s_out[2]$latch s_out[2] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 42.92 % ) " "Info: Total cell delay = 2.322 ns ( 42.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.088 ns ( 57.08 % ) " "Info: Total interconnect delay = 3.088 ns ( 57.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.410 ns" { s_out[2]$latch s_out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.410 ns" { s_out[2]$latch s_out[2] } { 0.000ns 3.088ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.607 ns" { clk state.su_open Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.607 ns" { clk clk~combout state.su_open Selector26~177 s_out[2]$latch } { 0.000ns 0.000ns 1.738ns 0.955ns 5.746ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.410 ns" { s_out[2]$latch s_out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.410 ns" { s_out[2]$latch s_out[2] } { 0.000ns 3.088ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "code2\[0\] res clk -2.082 ns register " "Info: th for register \"code2\[0\]\" (data pin = \"res\", clock pin = \"clk\") is -2.082 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns code2\[0\] 2 REG LC_X11_Y6_N2 6 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X11_Y6_N2; Fanout = 6; REG Node = 'code2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk code2[0] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk code2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout code2[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.122 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.122 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns res 1 PIN PIN_20 58 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 58; PIN Node = 'res'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { res } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.545 ns) + CELL(0.511 ns) 4.219 ns code2\[3\]~3 2 COMB LC_X11_Y6_N9 4 " "Info: 2: + IC(2.545 ns) + CELL(0.511 ns) = 4.219 ns; Loc. = LC_X11_Y6_N9; Fanout = 4; COMB Node = 'code2\[3\]~3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.056 ns" { res code2[3]~3 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(1.243 ns) 6.122 ns code2\[0\] 3 REG LC_X11_Y6_N2 6 " "Info: 3: + IC(0.660 ns) + CELL(1.243 ns) = 6.122 ns; Loc. = LC_X11_Y6_N2; Fanout = 6; REG Node = 'code2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.903 ns" { code2[3]~3 code2[0] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.917 ns ( 47.65 % ) " "Info: Total cell delay = 2.917 ns ( 47.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.205 ns ( 52.35 % ) " "Info: Total interconnect delay = 3.205 ns ( 52.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.122 ns" { res code2[3]~3 code2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.122 ns" { res res~combout code2[3]~3 code2[0] } { 0.000ns 0.000ns 2.545ns 0.660ns } { 0.000ns 1.163ns 0.511ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk code2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout code2[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.122 ns" { res code2[3]~3 code2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.122 ns" { res res~combout code2[3]~3 code2[0] } { 0.000ns 0.000ns 2.545ns 0.660ns } { 0.000ns 1.163ns 0.511ns 1.243ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 9 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 10 10:20:15 2008 " "Info: Processing ended: Fri Oct 10 10:20:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}