📄 code.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register one_key\[3\] register state.ss 51.2 MHz 19.532 ns Internal " "Info: Clock \"clk\" has Internal fmax of 51.2 MHz between source register \"one_key\[3\]\" and destination register \"state.ss\" (period= 19.532 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.057 ns + Longest register register " "Info: + Longest register to register delay is 9.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns one_key\[3\] 1 REG LC_X10_Y8_N4 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N4; Fanout = 12; REG Node = 'one_key\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { one_key[3] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.914 ns) 1.801 ns Equal8~58 2 COMB LC_X10_Y8_N8 17 " "Info: 2: + IC(0.887 ns) + CELL(0.914 ns) = 1.801 ns; Loc. = LC_X10_Y8_N8; Fanout = 17; COMB Node = 'Equal8~58'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { one_key[3] Equal8~58 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.589 ns) + CELL(0.200 ns) 4.590 ns Selector0~358 3 COMB LC_X11_Y7_N1 2 " "Info: 3: + IC(2.589 ns) + CELL(0.200 ns) = 4.590 ns; Loc. = LC_X11_Y7_N1; Fanout = 2; COMB Node = 'Selector0~358'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.789 ns" { Equal8~58 Selector0~358 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.078 ns) + CELL(0.200 ns) 6.868 ns Selector0~359 4 COMB LC_X11_Y8_N5 1 " "Info: 4: + IC(2.078 ns) + CELL(0.200 ns) = 6.868 ns; Loc. = LC_X11_Y8_N5; Fanout = 1; COMB Node = 'Selector0~359'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.278 ns" { Selector0~358 Selector0~359 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.511 ns) 8.161 ns Selector0~367 5 COMB LC_X11_Y8_N2 1 " "Info: 5: + IC(0.782 ns) + CELL(0.511 ns) = 8.161 ns; Loc. = LC_X11_Y8_N2; Fanout = 1; COMB Node = 'Selector0~367'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.293 ns" { Selector0~359 Selector0~367 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 9.057 ns state.ss 6 REG LC_X11_Y8_N3 7 " "Info: 6: + IC(0.305 ns) + CELL(0.591 ns) = 9.057 ns; Loc. = LC_X11_Y8_N3; Fanout = 7; REG Node = 'state.ss'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.896 ns" { Selector0~367 state.ss } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.416 ns ( 26.68 % ) " "Info: Total cell delay = 2.416 ns ( 26.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.641 ns ( 73.32 % ) " "Info: Total interconnect delay = 6.641 ns ( 73.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.057 ns" { one_key[3] Equal8~58 Selector0~358 Selector0~359 Selector0~367 state.ss } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.057 ns" { one_key[3] Equal8~58 Selector0~358 Selector0~359 Selector0~367 state.ss } { 0.000ns 0.887ns 2.589ns 2.078ns 0.782ns 0.305ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.511ns 0.591ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns state.ss 2 REG LC_X11_Y8_N3 7 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X11_Y8_N3; Fanout = 7; REG Node = 'state.ss'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk state.ss } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk state.ss } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout state.ss } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns one_key\[3\] 2 REG LC_X10_Y8_N4 12 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N4; Fanout = 12; REG Node = 'one_key\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk one_key[3] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk one_key[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout one_key[3] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk state.ss } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout state.ss } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk one_key[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout one_key[3] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.057 ns" { one_key[3] Equal8~58 Selector0~358 Selector0~359 Selector0~367 state.ss } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.057 ns" { one_key[3] Equal8~58 Selector0~358 Selector0~359 Selector0~367 state.ss } { 0.000ns 0.887ns 2.589ns 2.078ns 0.782ns 0.305ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.511ns 0.591ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk state.ss } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout state.ss } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk one_key[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout one_key[3] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 9 " "Warning: Circuit may not operate. Detected 9 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state.s3 s_out\[2\]\$latch clk 3.98 ns " "Info: Found hold time violation between source pin or register \"state.s3\" and destination pin or register \"s_out\[2\]\$latch\" for clock \"clk\" (Hold time is 3.98 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.788 ns + Largest " "Info: + Largest clock skew is 7.788 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.607 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns state.su_open 2 REG LC_X10_Y6_N7 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y6_N7; Fanout = 7; REG Node = 'state.su_open'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.032 ns" { clk state.su_open } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.955 ns) + CELL(0.511 ns) 5.661 ns Selector26~177 3 COMB LC_X10_Y6_N2 7 " "Info: 3: + IC(0.955 ns) + CELL(0.511 ns) = 5.661 ns; Loc. = LC_X10_Y6_N2; Fanout = 7; COMB Node = 'Selector26~177'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.466 ns" { state.su_open Selector26~177 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.746 ns) + CELL(0.200 ns) 11.607 ns s_out\[2\]\$latch 4 REG LC_X12_Y6_N4 1 " "Info: 4: + IC(5.746 ns) + CELL(0.200 ns) = 11.607 ns; Loc. = LC_X12_Y6_N4; Fanout = 1; REG Node = 's_out\[2\]\$latch'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.946 ns" { Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.168 ns ( 27.29 % ) " "Info: Total cell delay = 3.168 ns ( 27.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.439 ns ( 72.71 % ) " "Info: Total interconnect delay = 8.439 ns ( 72.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.607 ns" { clk state.su_open Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.607 ns" { clk clk~combout state.su_open Selector26~177 s_out[2]$latch } { 0.000ns 0.000ns 1.738ns 0.955ns 5.746ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.200ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns state.s3 2 REG LC_X9_Y6_N6 8 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y6_N6; Fanout = 8; REG Node = 'state.s3'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk state.s3 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk state.s3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.607 ns" { clk state.su_open Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.607 ns" { clk clk~combout state.su_open Selector26~177 s_out[2]$latch } { 0.000ns 0.000ns 1.738ns 0.955ns 5.746ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk state.s3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.432 ns - Shortest register register " "Info: - Shortest register to register delay is 3.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s3 1 REG LC_X9_Y6_N6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N6; Fanout = 8; REG Node = 'state.s3'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { state.s3 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.692 ns) + CELL(0.740 ns) 3.432 ns s_out\[2\]\$latch 2 REG LC_X12_Y6_N4 1 " "Info: 2: + IC(2.692 ns) + CELL(0.740 ns) = 3.432 ns; Loc. = LC_X12_Y6_N4; Fanout = 1; REG Node = 's_out\[2\]\$latch'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.432 ns" { state.s3 s_out[2]$latch } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.740 ns ( 21.56 % ) " "Info: Total cell delay = 0.740 ns ( 21.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.692 ns ( 78.44 % ) " "Info: Total interconnect delay = 2.692 ns ( 78.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.432 ns" { state.s3 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.432 ns" { state.s3 s_out[2]$latch } { 0.000ns 2.692ns } { 0.000ns 0.740ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.607 ns" { clk state.su_open Selector26~177 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.607 ns" { clk clk~combout state.su_open Selector26~177 s_out[2]$latch } { 0.000ns 0.000ns 1.738ns 0.955ns 5.746ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk state.s3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout state.s3 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.432 ns" { state.s3 s_out[2]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.432 ns" { state.s3 s_out[2]$latch } { 0.000ns 2.692ns } { 0.000ns 0.740ns } } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "one_key\[2\] num\[5\] clk 9.428 ns register " "Info: tsu for register \"one_key\[2\]\" (data pin = \"num\[5\]\", clock pin = \"clk\") is 9.428 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.914 ns + Longest pin register " "Info: + Longest pin to register delay is 12.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns num\[5\] 1 PIN PIN_103 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_103; Fanout = 5; PIN Node = 'num\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { num[5] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.698 ns) + CELL(0.740 ns) 4.570 ns Equal16~68 2 COMB LC_X9_Y8_N8 3 " "Info: 2: + IC(2.698 ns) + CELL(0.740 ns) = 4.570 ns; Loc. = LC_X9_Y8_N8; Fanout = 3; COMB Node = 'Equal16~68'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.438 ns" { num[5] Equal16~68 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 188 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.022 ns) + CELL(0.511 ns) 8.103 ns Equal16~69 3 COMB LC_X10_Y9_N2 1 " "Info: 3: + IC(3.022 ns) + CELL(0.511 ns) = 8.103 ns; Loc. = LC_X10_Y9_N2; Fanout = 1; COMB Node = 'Equal16~69'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.533 ns" { Equal16~68 Equal16~69 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 188 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.855 ns) + CELL(0.914 ns) 10.872 ns WideOr10~50 4 COMB LC_X9_Y8_N6 2 " "Info: 4: + IC(1.855 ns) + CELL(0.914 ns) = 10.872 ns; Loc. = LC_X9_Y8_N6; Fanout = 2; COMB Node = 'WideOr10~50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.769 ns" { Equal16~69 WideOr10~50 } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 184 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.804 ns) 12.914 ns one_key\[2\] 5 REG LC_X10_Y8_N2 12 " "Info: 5: + IC(1.238 ns) + CELL(0.804 ns) = 12.914 ns; Loc. = LC_X10_Y8_N2; Fanout = 12; REG Node = 'one_key\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.042 ns" { WideOr10~50 one_key[2] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.101 ns ( 31.76 % ) " "Info: Total cell delay = 4.101 ns ( 31.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.813 ns ( 68.24 % ) " "Info: Total interconnect delay = 8.813 ns ( 68.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.914 ns" { num[5] Equal16~68 Equal16~69 WideOr10~50 one_key[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.914 ns" { num[5] num[5]~combout Equal16~68 Equal16~69 WideOr10~50 one_key[2] } { 0.000ns 0.000ns 2.698ns 3.022ns 1.855ns 1.238ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.914ns 0.804ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 133 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 133; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns one_key\[2\] 2 REG LC_X10_Y8_N2 12 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N2; Fanout = 12; REG Node = 'one_key\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk one_key[2] } "NODE_NAME" } } { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 182 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk one_key[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout one_key[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.914 ns" { num[5] Equal16~68 Equal16~69 WideOr10~50 one_key[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.914 ns" { num[5] num[5]~combout Equal16~68 Equal16~69 WideOr10~50 one_key[2] } { 0.000ns 0.000ns 2.698ns 3.022ns 1.855ns 1.238ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.914ns 0.804ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk one_key[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout one_key[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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