code.tan.qmsg

有关键盘接口的程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "openlock\$latch " "Warning: Node \"openlock\$latch\" is a latch" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "s_out\[0\]\$latch " "Warning: Node \"s_out\[0\]\$latch\" is a latch" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "s_out\[1\]\$latch " "Warning: Node \"s_out\[1\]\$latch\" is a latch" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "s_out\[2\]\$latch " "Warning: Node \"s_out\[2\]\$latch\" is a latch" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "s_out\[3\]\$latch " "Warning: Node \"s_out\[3\]\$latch\" is a latch" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 230 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "WideNor0~12 " "Info: Detected gated clock \"WideNor0~12\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 233 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "WideNor0~12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state.s2 " "Info: Detected ripple clock \"state.s2\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "state.s2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state.s1 " "Info: Detected ripple clock \"state.s1\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "state.s1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state.s3 " "Info: Detected ripple clock \"state.s3\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "state.s3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state.s4 " "Info: Detected ripple clock \"state.s4\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "state.s4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state.su_open " "Info: Detected ripple clock \"state.su_open\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "state.su_open" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state.sa_open " "Info: Detected ripple clock \"state.sa_open\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "state.sa_open" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector26~177 " "Info: Detected gated clock \"Selector26~177\" as buffer" {  } { { "code.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/work1/code.vhd" 49 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector26~177" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}